Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1999-12-16
2003-12-23
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S001000, C365S189050, C365S120000
Reexamination Certificate
active
06668302
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to programmable technology generally, and more particularly, to a method and architecture for reprogramming conventionally non-reprogrammable technology.
BACKGROUND OF THE INVENTION
It is desirable to provide external programming of a pre-manufactured device in order to change the configuration after the device is manufactured. One way to provide a variety of programming options is to use a technology that can be programmed multiple times, such as an electrically erasable programmable read only memory (EEPROM). Another possibility would be to use external pins to select an unused page in a programmable array. Yet another possibility would be to use special packaging which would allow the electrically programmable array to be erased and re-programmed. Such a technology may include ultraviolet (UV) erasure of an electrically programmable read only memory.
A disadvantage with any of these methods is the fact that they require relatively complex technology to implement a programmable structure that can be written to more than one time. The method of providing additional pins increases the entire pin count of the device, which reduces the desirability of the technology. The possibility of providing a special package that allows a one-time programmable structure to be erased is also more complex than a traditional plastic package.
Referring to
FIG. 1
, a circuit
10
is shown implementing an EEPROM as a programmable memory. The circuit
10
generally comprises a number of internal components, an EEPROM portion
12
, one or more programming control inputs
14
and one or more outputs
16
. The output
16
may be, in an example of a clock generator circuit, an output clock. The internal components, in the example of a clock generator circuit, may be a PLL
18
, a PLL
20
and a miscellaneous logic block
22
. The programming control received at the input
14
is presented to an input
24
of the EERPOM
12
. The EEPROM
12
presents a signal to an input
28
of the miscellaneous logic block
22
. The miscellaneous logic block
22
presents an output
30
that presents a signal to the output
16
. Whatever function is implemented with the miscellaneous logic block
22
, the EEPROM
12
presents control information in response to configuration information received from the external inputs
14
. However, it would be desirable to replace the EEPROM
12
with a less complex one-time programmable technology without losing the ability to program the circuit
10
more than one time.
SUMMARY OF THE INVENTION
The present invention provides a method and architecture for allowing a device using a traditional one-time programmable technology to be programmed multiple times within the package. The present invention provides multiple programming without introducing the additional complexity of external pins or specialized packaging. An address counter and main array is provided using one-time programmable technology. The address counter selects a page in the main array to write the programmable information. The desired programming information is programmed into a first page while the additional pages remain unprogrammed. When additional information needs to be configured, the address counter is incremented and points to a new page in the main array where the new programming information may be stored. As a result, a number of programming configurations can be programmed into a one-time programmable technology. The advantages of erasable technology may be implemented using the simplicity of one-time programmable technology.
The object features and advantages of the present invention include providing a one-time programmable technology that may be programmed more than one time. The present invention does not incur the additional complexities of added external pins, special packaging or complex erasable technology.
REFERENCES:
patent: 4970418 (1990-11-01), Masterson
patent: 5264689 (1993-11-01), Maes et al.
patent: 5418960 (1995-05-01), Munroe
patent: 5684434 (1997-11-01), Mann et al.
patent: 5740112 (1998-04-01), Tanaka et al.
Kornacki, W.E. “The Partial Reprogramming of EPROMs”, Electronic Engineering, vol. 57, No. 698, p. 43, Feb. 1985.
Cypress—Understanding the CY2291 and CY2292 7-22 to 7-29.
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Thai Tuan V.
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