Method and architecture for power management of an...

Details Method and architecture for power management of an... Method and architecture for power management of an...

2007-08-29

2010-11-09

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07831935

ABSTRACT:
A method of reducing static power consumption in a low power electronic device. The electronic device including one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional circuit connected between the local power grid and the local ground grid; a global storage capacitor coupling a global power grid to a global ground grid, each local ground grid connected to the global ground grid; one or more switches, each switch selectively connecting the global power grid to a single and different corresponding local power grid; and a power dispatch unit adapted to open and close the one or more switches.

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