Method and architecture for power management of an...

Details Method and architecture for power management of an... Method and architecture for power management of an...

2006-03-31

2008-11-18

Butler, Dennis M (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S320000

Reexamination Certificate

active

07454642

ABSTRACT:
A method of reducing static power consumption in a low power electronic device. The electronic device including one or more power islands, each power island including: a local storage capacitor coupling a local power grid to a local ground grid; and a functional circuit connected between the local power grid and the local ground grid; a global storage capacitor coupling a global power grid to a global ground grid, each local ground grid connected to the global ground grid; one or more switches, each switch selectively connecting the global power grid to a single and different corresponding local power grid; and a power dispatch unit adapted to open and close the one or more switches.

REFERENCES:
patent: 6861739 (2005-03-01), Bhavnagarwala et al.
patent: 2005/0213267 (2005-09-01), Azrai et al.
patent: 2005/0213280 (2005-09-01), Azrai et al.
patent: 2006/0006929 (2006-01-01), Caplan et al.
patent: 2006/0123365 (2006-06-01), Hoberman et al.
patent: 2006/0208574 (2006-09-01), Lasseter et al.

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