Method and architecture for non-sequentially programming one-tim

Details Method and architecture for non-sequentially programming one-tim Method and architecture for non-sequentially programming one-tim

1996-10-17

1999-12-21

Thai, Tuan V.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711 1, 36518905, 365120, G06F 1200

Patent

active

06006305&

ABSTRACT:
The present invention provides a method and architecture for allowing a device using a traditional one-time programmable technology to be programmed multiple times within the package. The present invention provides multiple programming without introducing the additional complexity of external pins or specialized packaging. An address counter and main array is provided using one-time programmable technology. The address counter selects a page in the main array to write the programmable information. The desired programming information is programmed into a first page while the additional pages remain unprogrammed. When additional information needs to be configured, the address counter is incremented and points to a new page in the main array where the new programming information may be stored. As a result, a number of programming configurations can be programmed into a one-time programmable technology. The advantages of erasable technology may be implemented using the simplicity of one-time programmable technology.

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Kornacki, W.E., "The Partial Programming of EPROMs", Electronic Engineering, vol. 57, No. 698, p. 43, Feb. 1985.
Cypress--Understanding the CY2291 and CY2292 7-22 to 7-29.

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