Method and apparatus utilizing a region based page table walk bi

Details Method and apparatus utilizing a region based page table walk bi Method and apparatus utilizing a region based page table walk bi

1996-11-12

1998-09-15

Lane, Jack A.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711206, G06F 1210

Patent

active

058095632

ABSTRACT:
A method and an apparatus for translating a virtual address into a physical address in a multiple region virtual memory environment. In one embodiment, a translation lookaside buffer (TLB) is configured to provide page table entries to build a physical address. The TLB is supplemented with a virtual hash page table (VHPT) to provide TLB entries in the occurrences of TLB misses. An alternate software replacement scheme may be utilized on a per region basis instead of the default page table walk of the VHPT with a dedicated bit associated with each particular region of the disclosed virtual address space. A VHPT walk is performed only if the particular bit for the particular region and a master enable bit are both enabled. Otherwise, the alternate software replacement routine is performed to provide TLB replacements in the occurrences of TLB misses.

REFERENCES:
Gregg Wyant & Tucker Hammerstrom, How Microprocessors Work, 98-103 (1994).
PowerPC 601 RISC Microprocessor User's Manual, Chapter 6: Memory Management nit, Motorola Inc. (1993).

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