Method and apparatus using address and read head location inform

Details Method and apparatus using address and read head location inform Method and apparatus using address and read head location inform

1997-06-16

1999-01-12

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711112, G06F 1200

Patent

active

058601031

ABSTRACT:
Minimal random disk write latency is achieved by limiting the number of logical address blocks that can be serviced by a disk to less that the actual number of physically addressable blocks of the system and having a disk controller dynamically map logical data blocks to physical disk blocks in such a fashion that each logical write can take place to any free location, where the free location can be chosen in any track of the current cylinder.

REFERENCES:
patent: 4467421 (1984-08-01), White
patent: 4536837 (1985-08-01), Olson et al.
patent: 5124987 (1992-06-01), Milligan et al.
patent: 5206939 (1993-04-01), Yanai et al.
patent: 5359611 (1994-10-01), Parks et al.
patent: 5408644 (1995-04-01), Schneider et al.

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