Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2004-03-10
2008-08-19
Nguyen, T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S144000
Reexamination Certificate
active
07415577
ABSTRACT:
Briefly, in accordance with an embodiment of the invention, a method and apparatus to write back data is provided. The method may include setting a status corresponding to a block of data in response to a change in address mapping to indicate that the block of data is pending write back. The apparatus may include a storage area to store a status associated with a block of data to indicate that the block of data is pending write back and is not accessible with the current address mapping. Other embodiments are described and claimed.
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patent: 6564301 (2003-05-01), Middleton
patent: 7076613 (2006-07-01), Peir et al.
John L. Hennessy, et al., “Computer Architecture”, A Quantitative Approach, 3rd Addition 2003, pp. 390-402, 460-465, 549-554.
Intel Corporation
Nguyen T
Wheeler Cyndi M.
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