Method and apparatus to steer memory access operations in a...

Details Method and apparatus to steer memory access operations in a... Method and apparatus to steer memory access operations in a...

2005-06-28

2005-06-28

Ellis, Kevin L. (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address multiplexing or address bus manipulation

Reexamination Certificate

active

06912644

ABSTRACT:
A memory management unit (MMU) includes a translation look-aside buffer (TLB) that stores memory access steering data within corresponding TLB entries for use in steering memory access operations.

REFERENCES:
patent: 5946716 (1999-08-01), Karp et al.
patent: 6286091 (2001-09-01), Park
patent: 6681311 (2004-01-01), Gaskins et al.
patent: 6704854 (2004-03-01), Meier et al.

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