Electrical computers and digital processing systems: memory – Address formation – Operand address generation
Reexamination Certificate
1996-10-23
2001-09-18
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Address formation
Operand address generation
C711S003000, C711S141000, C711S200000
Reexamination Certificate
active
06292879
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to digital processing systems, more specifically, concerning identifying data coherency requirement and data caching requirement, with a piece of data residing in one or more different storage elements in a digital data processing system, providing access control code of a piece of data which relates more particularly to digital data processing systems with multiprogramming, and a mixed static and dynamic branch prediction method with correct static branch predictions on both in-loop (during looping) and loop-exit (exit from loops) branch predictions.
2. Description of the Prior Art
A digital data processing system (computer) instruction is composed of an opcode and one or more operands. The operands are data in either registers or memory. There are no qualifiers that explicitly specify the nature and system attributes for the data except those implied by the opcode. In a descriptor architecture computer, the operands in an instruction are specified by descriptors. A descriptor of an operand usually consists of a virtual address of the memory space of the operand, its data type and size, and vector specification if so exists.
To optimize the memory reference performance, operating systems specify if a page of data should be encached or not, so that unnecessary and undesirable data encaching will be avoided. It is also desirable to be able to specify if maintaining data coherency in a multiprocessing system is required. Such maintenance demands exhaustive checking, which creates performance bottlenecks and system complexity, but only a small percentage of data requires absolute data coherency. To provide protection to data, access code is often utilized to limit read, write and sometimes execution accesses to authorized and privile,ed processes.
At present, to specify a piece of data in a digital data processing system the system attributes such as encaching or maintaining data coherency, and access control of the piece of data, is on page basis through Translation Lookaside Buffer (TLB) via page table entries in page tables managed by memory management of operating systems. The data coherency is normally assumed to be required in a computer system. The access control on data is normally on per page basis and is implemented in the Translation Lookaside Buffer (TLB) via page tables managed by memory management of operating systems.
At present, in descriptor architecture computers, just like in others, system attributes such as access control on data, caching options to specify if a page of data should be encached or not, and ability to specify if maintaining absolute data coherency in a multiprocessing system is required, are on per page basis and not on individual operands.
The present computers contain branch prediction logic to predict with high accuracy if branching will take place for a conditional branch instruction or not. It is done so with static and dynamic branch prediction schemes. Static methods are based on compilers to generate object codes to identify to the processor if branching is likely or unlikely to occur. Dynantic methods are based on hardware to store histogram of earlier branching and not branching actions, and make an educated guess that branching will be talcen or not, for the current conditional branch instruction.
The present invention is an improvement over certain previous computer systems. An instruction consists of an opcode, and indexes of operand descriptors pointing to operand descriptors as a descriptor computer, and a branch prediction scheme.
SUMMARY OF THE INVENTION
The invention disclosed herein concerns features that add to the existing processors, described in the previous section of “Description of the Prior Art”. These features are parts of the computer system HISC: A High-level Instruction Set Computer.
The first feature is the indicator or data coherency flag residing in the operand descriptor that indicates if it is required to maintain the coherency of the data when the data is stored in various storage elements or caches in a processing system. The requirement will typically be accomplished by a method checking the existing data of the address in other storage elements in the processing system, which typically are caches, and buffers. The benefit of this invention is to eliminate the need of such checking for the operands that are specified to have no such need of maintaining absolute data coherency, to minimize the snooping necessary for data coherency. The decision on issuing such data coherency flag is accomplished trough programming languages and their corresponding compilers.
There is also an indicator or eneaching flag residing in the operand descriptor that indicates if the data is to be encached or not. Encaching means the data will also resides in cache, in order to expedite the accesses to the data. However, there are cases that this facility is not desirable, such as in those cases the references will be made only once for a long time. This feature is to avoid unnecessary or undesirable caching.
Another invention feature is the access control code in the operand descriptor which indicates the access privilege required in order to be able to perform certain access to the data, together with the required mode of the accessor. The access is defined as read, write and/or execute, and the mode is either supervisor and user. The supervisor mode dictates that only supervisor processes can access the data of the operand if other access code bits permit. A non-supervisor (or user) mode indicates that all processes can access the data provided that other access code bits permit.
The branch prediction of HISC is a mix of dynamic and static branch prediction method. The static part is done through the opcode assignment In HISC, an instruction consists of a 16-bit opcode, followed by three 16-bit operand descriptors, as shown in FIG.
1
. Two bits in the opcode field are used to facilitate conditional branching. The first of the two bits is used to indicate if static conditional branch prediction or dynamic branch prediction is used. The second bit is for static branch prediction to indicate prediction of branching. The compiler will decide if the static or the dynamic branch prediction should be used, and in static branch prediction case, if it is likely or unlikely to branch. Inner loop counting will utilize the static prediction, and the opcode will indicate if it is likely to branch or not. For other conditional branching which will mainly be decision making, the dynamic branch prediction is used. In order to identify the last pass of a loop counting, the Branch Prediction Unit (BPU) of HISC contains a fully-associative array, a loop-exit look-up table, of addresses of static prediction branch instructions of loop counting. There is a special loop-counting instruction in HISC. BPU will put the current branch instruction address into the associative array when it detects the loop-counting instruction and it is executing the second last pass. If BPU encounters a hit in the loop-exit look-up table, it will predict the opposite of the static prediction scheme, since this is the very last pass of the loop. If the addresses overflow the look-up table capacity, the incorrect prediction only impacts the performance. If there is any entry in the array is replaced undesirably, the processor still maintains its system integrity.
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Law Offices of Jonanthan Alan Quine
LeBlanc Stephen J.
Thai Tuan V.
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