Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-05-19
2003-02-11
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S034000
Reexamination Certificate
active
06519721
ABSTRACT:
BACKGROUND
FIELD
The invention relates to software security and, more particularly, to reducing the risk of unwanted observation of a program's operation.
BACKGROUND INFORMATION
A software program typically includes a sequence of instructions stored in a memory and executed by a processor. As used herein, the term “program” may refer to any form of packaging (that is, organizing and grouping) sequences of software instructions. The term “program” may refer to executable programs, statically-linked libraries, dynamically-linked libraries, applets, and many other forms of packaging and organization for software sequences well known in the art.
It is often desirable to make it more difficult for unauthorized persons to observe the operation of a program. This may be done to protect trade secrets or to help prevent unauthorized copying of the program, among other reasons. Many techniques exist for this purpose. One such technique involves applying data signals external to a program to affect the execution of the program. During program execution, the external data signals are read by the program from an external memory and applied to determine the execution flow of the program, decrypt instructions or data employed during execution, or to test the integrity of the program. The data signals may be stored in the external memory as digital binary signals, e.g. bits, in manners well known in the art.
Unauthorized third parties may attempt to ascertain a program's operation by inspecting a static listing of the sequence of instructions in the program. A static listing, in this context, is a listing of the instructions in the program while the program is not executing on a processor. For example, a disassembler may be employed to list the instructions of the non-executing program. When the execution of the instructions is determined by data signals read at execution time, a person employing a disassembler may be unable to determine the program's operation from the static listing.
One disadvantage to this technique is that a third party employing an execution-time debugger may step through the program once the external data is read to observe the program's operation. Debuggers typically rely upon certain features of the processor to enable their operation. For example, the processor may support a “break point” interrupt to assist the debugger in pausing program execution when a selected instruction address is encountered. For example, the Intel Pentium® processor employs the INT 3 instruction for such a purpose. The processor may provide a “step” interrupt to assist the debugger in stepping through program execution one instruction at a time, and the processor may comprise special debug registers for specifying instruction addresses or memory locations at which program execution may be paused.
Some processors may support the disabling of debug support by executing a special instruction. Disabling processor debug support results in the processor not supporting one or more of such debug facilitating features. Such disabling of debug support is typically temporary until such time as the same or another program in the system executes an instruction to re-enable debug support.
It would be advantageous to increase the level of difficulty for persons attempting to ascertain the operation a program using static listings or run-time debuggers.
SUMMARY
Debug support for a program is first disabled such that debug support can not be re-enabled for the program until execution of the program by a processor terminates. Data signals external to the program are then read to determine program operation.
REFERENCES:
patent: 5446864 (1995-08-01), Burghardt et al.
patent: 6006328 (1999-12-01), Drake
patent: 6061518 (2000-05-01), Hoffman
patent: 6076149 (2000-06-01), Usami et al.
patent: 6182208 (2001-01-01), Peri et al.
patent: 6237137 (2001-05-01), Beelitz
patent: 6249881 (2001-06-01), Porten et al.
patent: 6272636 (2001-08-01), Neville et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Iqbal Nadeem
LandOfFree
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