Method and apparatus to reduce power consumption on a bus

Details Method and apparatus to reduce power consumption on a bus Method and apparatus to reduce power consumption on a bus

2000-03-06

2001-08-28

Etienne, Ario (Department: 2155)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S324000

Reexamination Certificate

active

06282665

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to the field of digital systems, and, more particularly, to reducing the power requirements of digital systems. Specifically, the invention relates to a method and apparatus for reducing the power consumed by a bus.
2. Description of the Related Art
With the growing complexity of modern computer systems, designers are constantly seeking more efficient methods to reduce power consumption. Modem computer systems may contain several microprocessors, microcontrollers, and other digital devices connected to each other by a bus. The bus transports data among the microprocessors and other components, and is composed of a number of wirelike connections that function as information-transfer lines, which may be located on a “motherboard” (i.e., main printed circuit board).
A “bus node” or “node,” as used in the art, comprises a set of functional entities (e.g., a memory, processor, etc.) which share a common interface to a bus (e.g., the IEEE 1394-1995 serial bus).
FIG. 1A
illustrates a nodal configuration for a 1394 “node”
100
, which consists of a 1394 bus interface
101
together with one or more “units” (e.g., disk drives, modems, computers, etc.)
102
, which share the node's common bus interface
101
. One skilled in the art would appreciate that the node
100
may also include other types of logic circuits that have not been shown.
FIG. 1A
also indicates that the bus interface
101
consists of two subsections, one of which is a “physical layer” or “PHY”
103
, which provides an electrical bus interface. The physical layer
103
includes one or more bus “ports”
104
, which are connection points for bus cable segments
105
. Collectively, the bus cable segments
105
constitute a 1394 bus (not shown).
The other layer within the bus interface circuit
101
is a “link layer” or “link”
106
, which provides a packet interface between the physical layer
103
and the node's unit(s)
102
. The link
106
layer may be used to analyze the data within a received request to determine if one of its local units is the targeted (i.e., destination) unit. If so, the link layer
106
would forward the request to the targeted unit. In any event, the physical layer
103
, retransmits the signal on the bus to all ports. A 1394 bus consists of a collection of port-to-port connections between physical layers of several nodes, with each node providing internal signal routing between the ports on that physical layer.
FIG. 1B
illustrates a notebook computer
100
with a hard disk drive
111
connected by a cable
112
. The hard disk drive
111
is connected to a printer
113
by a cable
114
, and the printer
113
is connected to a scanner
115
by cable
116
. The notebook
110
is also connected to a Compact Disk or DVD drive
120
by a cable and to a digital camera
125
by cable
126
. The cables
106
,
111
,
116
,
121
,
126
are cables in a bus (e.g., IEEE Std 1394-1995) that has point-to-point connections, which allows these devices to be connected to one another in any desired configuration. A 1394 bus, for example, may also be used to connect internal devices to a platform (e.g., connecting an internal primary hard disk to the notebook computer
110
).
Point-to-point connections enable communication to occur by having intermediate devices forward information to the desired receiving device. For example, if a picture was scanned into the scanner
115
to be stored on the CD-ROM
120
, the scanner would forward the data to the printer
113
(as well as to any other device which might be attached to another port on the scanner). The printer
113
would forward the data to the hard disk drive
111
, which would forward the data to the notebook
110
and then to the CD-ROM
120
. One skilled in the art will appreciate that even though the data was not directed to the printer
113
, hard disk drive
111
, or notebook
111
, each plays a role in making sure that the data arrives at the intended destination.
In
FIG. 2A
, a node
200
includes three units
205
-
207
connected to a link logic circuit
210
by the cables
208
. The physical layer
215
includes three ports
216
-
218
, which enable the node
200
to be connected to as many as three other nodes. One skilled in the art will appreciate that the other physical layers illustrated include more or fewer ports than the three illustrated here.
FIG. 2B
illustrates a connection of the node
200
to nodes
220
,
230
, and
240
. Specifically, the ports
216
,
218
are connected to ports
221
and
231
within the nodes
220
and
230
, respectively. The port
217
is coupled to a port
243
of the node
240
; the port
251
of node
250
is also connected to port
241
of node
240
.
As previously mentioned, each of the nodes
220
,
230
,
240
,
250
contain a link layer and a physical layer. For example, the node
250
includes the unit devices
255
-
257
, the link logic circuit
252
, and the physical layer
254
. Though most
1394
nodes include at least one unit, certain nodes may contain only a physical-layer circuit. Such “naked PHY” nodes are often useful in relaying and electrically redriving bus traffic, even though these nodes do not generate or accept their own bus traffic, except as a signal relay.
Observation of
FIG. 2B
reveals that there is no single cable that connects one node to all of the other nodes. For example, the node
250
is not directly connected to the nodes
200
,
220
,
230
, thereby illustrating the “point-to-point” nature of this type of bus. If the node
200
desires to send data to the node
250
, one of the unit devices
205
-
207
would send the data to the link logic circuit
210
. The link logic circuit
210
would send a signal to the physical-layer circuit
215
, which would apply that signal to the bus via all of the ports
216
-
218
. The signal travels to the ports
221
,
231
,
243
of the physical layer of nodes
220
,
230
,
240
, respectively. The physical layers
224
,
234
,
244
corresponding to the ports
221
,
231
,
243
forward the signal to their associated link logic circuits
222
,
232
,
242
. These link logic circuits then determine if the packet is addressed to one of their local unit devices (e.g., unit devices
245
-
247
). If so, then each link circuit passes the packet to that link's targeted unit(s).
If, for example, a packet is received through port
243
of physical layer
244
, it is retransmitted through ports
241
and
248
. In addition, the incoming packet is sent to link logic circuit
242
which determines, through packet address-matching, whether the incoming packet is directed to one of this node's local units
245
-
247
. If so, the link logic circuit
242
then sends the packet to the targeted unit, as well as producing an acknowledgement packet that is sent out through all of node
240
's physical ports. In this way, the acknowledgement is forwarded by the node
240
and thus arrives at the original packet source node (i.e., the node
200
).
Because some of the nodes function as forwarding mechanisms during the transmission of data on the bus, and due to the point-to-point nature of the bus, it becomes desirable to have both the physical layer and the link logic circuit powered during transmission. When the IEEE 1394-1995 protocol was developed, it was developed with the condition that the physical layer and the link logic circuit remain powered at all times. Some “cable-powered” 1394 devices acquire power for the link layer and/or physical layer from the bus. Alternatively, “self-powered” devices power the local link layer and physical layer from a resident power source, such as a battery or local AC supply (“AC brick”).
If, for example, node
200
is providing power for the link circuit
210
and the physical layer
215
, then those circuits are said to be powered “locally.” Such a node may need to remain fully powered in order to properly power the link logic circuit
210
and the physical layer
215
, even when the unit(s) on that

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