Method and apparatus to power down unused configuration...

Details Method and apparatus to power down unused configuration... Method and apparatus to power down unused configuration...

2005-07-29

2009-06-16

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C326S039000

Reexamination Certificate

active

07548091

ABSTRACT:
A method for reducing power consumption for a programmable logic device (PLD) is provided. In the method, configuration cells associated with used logic portions of the PLD are powered. A programmable power signal preventing source to drain leakage is provided to an inverter of a configuration random access memory (CRAM) cell associated with an unused logic portion of the PLD. The programmable power signal deactivates at least a portion of a configuration cell associated with the unused logic portion. That is, the programmable power signal eliminates the source to drain leakage as the power provided to the configuration cell is at ground. In one embodiment, the programmable power signal is provided to both inverters of a cross coupled pair of inverters rather than a single one of the cross-coupled pair of inverters. A programmable logic device capable of minimizing standby power consumption is also included.

REFERENCES:
patent: 6101143 (2000-08-01), Ghia
patent: 7026840 (2006-04-01), May et al.
patent: 2005/0035782 (2005-02-01), Swami

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