Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-06-24
2004-09-07
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06789248
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to computing methods and systems that facilitate electronic design automation of integrated circuitry. More specifically this invention is related to methods and apparatus that adjust resistance and capacitance parameters in a library database containing a description of circuits and constraints of an integrated circuit fabricating process. The library database is used in a physical synthesis program module of a design automation system.
2. Description of Related Art
The structure of the methods and systems used to design and prepare an integrated circuit for fabrication is well known in the art. Referring to
FIG. 1
, the integrated circuit design begins with creation (Box
100
) of a high-level circuit spefication. The high-level circuit specification details the function of the integrated circuit, and the constraints of the integrated circuit such as physical size, voltage levels, current levels, power dissipation, frequency, and environmental factors (temperature, etc.). The circuit function is translated to a logic design written in a hardware description language such as VHDL (Very High Speed Integrated Circuit Hardware Description Language) or Verilog Hardware Description Language.
Generally, the structure of the integrated circuit is in register transfer language (RTL) and the hardware descriptor language is structured as the RTL code (Box
105
). The RTL code (Box
105
) is transferred to a program system that generates or synthesizes (Box
110
) a circuit or gate level design from the hardware description of the integrated circuit. The logic synthesis (Box
110
) provides the initial description of the physical structure that the integrated circuit is to have. The logic synthesis (Box
110
) in what is termed timing driven design performs a rough estimate of the delays of each circuit of the design including the intrinsic delay of each circuit and an estimate of the timing delays caused by the interconnecting wiring. The logic synthesis (Box
110
) employs a wire load model (WLM) (Box
115
) to provide an estimate of the timing delays that result from the interconnecting wiring.
The wire load model is a statistical model that provides an estimate of wiring length for a path based on the type of path (long path, short path, control logic, functional logic, array data path, or array control path) and some historic statistics for the particular circuit path types. Further, it is known that certain functions will be grouped and therefore circuit paths within a function have one estimated length while inter-function circuit paths will have a different length (longer). Based on the statistical data and certain constraints and estimates, the logic synthesizer can provide a rough prediction of the timing delays for the circuit paths of an integrated circuit.
Once the logic synthesis (Box
110
) is completed, the circuits are then placed (Box
120
) based on the constraints developed in the design specification (Box
100
) and during the logic synthesis (Box
110
). After the circuits are placed (Box
120
), the interconnecting wiring is routed (Box
125
). This defines the actual structure of each segment of the printed circuit wiring of the integrated circuit. The wiring is generally placed on multiple levels and is routed in horizontal and vertical directions depending on the level of the wire routing.
The completed wire routing description is used to extract (Box
130
) the resistance and capacitance values for each segment of all the wiring interconnections of the integrated circuit. This is the first opportunity for a true statistical timing analysis to determine the performance of the integrated circuit. The resistance and capacitance of each segment of the interconnecting wiring is generally determined employing a three-dimensional solver. The three dimensional solver calculates the resistance of the segments based on the cross-sectional area and length of each segment and the resistivity (&rgr;) of the interconnecting wiring segments. The three dimensional solver calculates the capacitance based on the surface area of the wiring, the distance to the adjoining wiring segments or the semiconductor substrate, and the dielectric constant (&egr;) of the intervening insulator. These calculated resistances and capacitances are relatively accurate and allow a timing analysis (Box
135
) that predicts the performance of the integrated circuit precisely within the bounds of the process variations. The design of the integrated circuit is evaluated (Box
140
) to establish if the design complies with the design specification. If the design specification is not met the design is appropriately modified (Box
145
) and the process repeated. If the design complies with the specification, the design is then fabricated (Box
150
)
It is well known in the art that, as the lithography of the semiconductor processing has improved to allow minimum feature size to decrease from 0.5 &mgr;m to 0.25 &mgr;m to approaching 0.18 &mgr;m and event to 0.1 &mgr;m, the proportion of the delay of a circuit path that is attributable to the interconnections has increased. The increase has been from approximately 20% at 0.5 &mgr;m to approximately 45% at 0.25 &mgr;m to approximately 60% at 0.18 &mgr;m and smaller. Further, as shown in
FIG. 4
a
, the error in the capacitance used by the WLM model to estimate the path delay at the logical synthesis versus the actual capacitance as determined during the resistance and capacitance extraction (Box
130
) is greater than +/−20% (region A) for more than 50% of the paths of the integrated circuit. When the timing delay that resulted from the interconnections was a smaller proportion of the total path delay, the error had less an impact than when the interconnections become the dominant component of the total path delay.
Logical synthesis provided a logical design with only rudimentary consideration to the physical structure of the integrated circuit To refine the estimate of timing delay and its impact on performance of the integrated circuit logical synthesis, logical synthesis was replaced with physical synthesis. Refer now to
FIG. 2
for a discussion of an electronic design automation process. The design specification is created essentially as described above, with creation (Box
100
) of a high-level circuit specification. The high-level circuit specification details the function of the integrated circuit, and the constraints of the integrated circuit such as physical size, voltage levels, current levels, power dissipation, frequency, and environmental factors (temperature, etc.). The high-level circuit specification is then translated (Box
105
) to the Register Transfer Language Coding. The RTL coding (Box
105
) is not complete as in the Electronic Design process of FIG.
1
. Newly designed circuit functions are described functionally, without the detailed RTL coding. Current integrated circuit designs further have predesigned circuit functions such as memory arrays, microprocessors, etc.
The integrated circuit design is partitioned (Box
200
) to allocate the functional units of the integrated circuit design to unique physical areas of the substrate onto which the integrated circuit is to be fabricated. The circuit specification contains certain performance and timing criteria that are to be achieved by the integrated circuit. These timing and performance constraints are then budgeted (Box
205
) and allotted to the appropriate functional units of the integrated circuit design.
The RTL coding (Box
105
) is now transferred to a physical synthesizer to create the initial schematic description of the integrated circuit. Physical synthesis (Box
210
), as described in “Physical Synthesis: Design Tools and Flows for Sub-Micron, System-On-a-Chip Design Implementation,” Synopsis, Inc., Mountain View Calif., May 1999, brings key physical functions into the front-end process that allow an integrated circuit design to have the impact of the physical implementation
Chen Yee-Wen
Cheng Chia-Lin
Hou Cliff
Huang Hsing-Chien
Lu Lee-Chung
Do Thuan
Knowles Billy
Taiwan Semiconductor Manufacturing Company
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