Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Patent
1996-11-15
1998-06-09
Moore, David K.
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
711211, 39520001, 395280, 39518203, 395288, 395841, 395290, G06F 1210, G06F 922
Patent
active
057652171
ABSTRACT:
Method and apparatus for performing bus reflection operation using a data processor (10). The present invention allows a multiplexed peripheral bus master (16) to interface with non-multiplexed peripherals (12, 14) by using a data processor (10) to reflect an address value from the data bus (20) to the address bus (18), or alternately, from the address bus (18) to the data bus (20). In one embodiment, external bus master (16) provides the reflect request signal (30) to data processor (10), and in response, data processor (10) receives the address value provided by external bus master (16) on data bus (20) and drives this same address value on address bus (18) to memories (12, 14). In addition, the present invention allows an external bus master (16) to use the handshake circuitry (50) on data processor (10) to interface with peripheral devices (12,14).
REFERENCES:
patent: 5086407 (1992-02-01), McGarity et al.
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patent: 5146592 (1992-09-01), Pfeiffer et al.
patent: 5448719 (1995-09-01), Schultz et al.
Motorola, Inc.; "MC68302 Integrated Multiprotocol Processor User's Manual; Second Edition;" 1991; Section: System Integration Block (SIB); pp. 3-1 through 3-75.
Hill Susan C.
Moore David K.
Motorola Inc.
Nguyen Than V.
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