Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Depositing predominantly single metal or alloy coating on...
Reexamination Certificate
2001-05-10
2004-10-26
Koehler, Robert R. (Department: 1775)
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Depositing predominantly single metal or alloy coating on...
C205S103000, C205S123000, C205S157000, C205S799000
Reexamination Certificate
active
06808612
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electrochemical deposition or electroplating of a metal onto a substrate. More particularly, the invention relates to a method for electrochemical deposition of a metal into high aspect ratio structures on a substrate.
2. Background of the Related Art
Sub-quarter micron, multi-level metallization is one of the key technologies for the next generation of ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines, dual damascenes, and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
As circuit densities increase, the widths of vias, contacts, dual damascenes, and other features, as well as the dielectric materials between them, decrease to less than 250 nanometers, whereas the thickness of the dielectric layers remains substantially constant, with the result that the aspect ratios for the features, i.e., their height divided by width, increases. Many traditional deposition processes, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), have difficulty filling structures, such as dual damascenes, where the aspect ratio exceed 4:1, and particularly where it exceeds 10:1. Therefore, there is a great amount of ongoing effort being directed at the formation of void-free, nanometer-sized features having high aspect ratios wherein the ratio of feature height to feature width can be 4:1 or higher. Additionally, as the feature widths decrease, the device current remains constant or increases, which results in an increased current density in the feature.
Currently, copper and its alloys have become the metals of choice for sub-quarter-micron interconnect technology because copper has a lower resistivity than aluminum, (1.7 &OHgr;-cm compared to 3.1 &OHgr;-cm for aluminum), and a higher current carrying capacity and significantly higher electromigration resistance. These characteristics are important for supporting the higher current densities experienced at high levels of integration and increased device speed. Further, copper has a good thermal conductivity and is available in a highly pure state.
Despite the desirability of using copper for semiconductor device fabrication, choices of fabrication methods for depositing copper into very high aspect ratio features, such as a 4:1 aspect ratio via having a width of 0.35&mgr; or less, are limited. As a result of these process limitations, electroplating, which had previously been limited to the fabrication of lines on circuit boards, is just now being used to fill vias and contacts on semiconductor devices.
Electroplating processes deposit a material on a conductive surface by the chemical reduction of metal ions in a chemical solution by the application of an external electrical current. However, electroplating processes require a conductive surface, such as a conductive barrier layer being deposited on a substrate surface prior to electroplating. The conductive barrier layer may be deposited by physical vapor deposition techniques or chemical vapor deposition techniques. Additionally, such barrier layer materials as titanium, tantalum and nitrides thereof, often do not provide a sufficiently conductive surface for deposition and a “seed” layer is deposited to provide adequate nucleation of an electroplating layer.
Electroplating processes typically require the electrically conductive nucleation, or seed, layer, to be thin and conformally deposited on the substrate to provide a surface on the substrate to adequately initiate the electroplating process. The seed layer typically comprises a conductive metal, such as copper, and is conventionally deposited on the substrate using physical vapor deposition (PVD) or chemical vapor deposition (CVD) techniques. It has been found that conformal deposition of the seed layer results in good electroplating of the substrate. However, as feature sizes decrease, the ability to deposit conformal seed layers can be compromised.
For example, the thin seed layer may not be deposited uniformly on the substrate. Uneven deposition of the seed layer can result in layer agglomeration or create a discontinuous layer over portions of the substrate and in the features formed on the substrate. Non-uniform deposition and agglomeration of the seed layer can result in a current that is not evenly distributed over the surface of the seed layer and may result in non-uniform deposition of subsequent electrochemical deposited layers on the substrate. The non-uniform deposition of subsequent layers has been observed to be detrimental to circuit uniformity, conductivity, and reliability. Furthermore, the non-uniformity and agglomeration of the seed layer may also reduce the effective adhesion of conductive material, such as copper, to the substrate and reduces the ability of subsequent layers to adequately bond to the conductive material.
FIG. 1
illustrates discontinuous and agglomeration defects from non-uniform deposition of a seed layer in a high aspect ratio feature
106
on a substrate
100
. Agglomerations
102
can form in feature
106
due to excess deposition of conductive materials, such as copper, on the sidewalls or bottom of the feature. The agglomeration may be extensive enough to “bridge” over a section of the feature
106
during subsequent deposition processes, such as electroplating, and form a void (not shown) inside the feature
106
. Additionally, discontinuities, such as voids
104
can form on the sidewalls and bottom of the feature
106
from non-uniform current densities. The discontinuities may detrimentally affect subsequent processing, such as by interfering with the application of uniform current densities along the feature surface during subsequent electroplating processes. This lack of uniform current densities on the seed layer may result in the formation of voids (not shown) on the sidewalls and bottoms of features in material deposited by electroplating processes.
Formation of voids and other filling defects in substrate structures from non-uniform or agglomerated layers is further compounded as the industry transitions from manufacturing 200 mm substrates to 300 mm substrates, where the variation in the uniformity of the deposited material can be greater. In electroplating copper films on 300 mm substrates, it has been observed that the uniformity of thin metal layers, such as seed layers used in electroplating processes, can be quite variable and the continuity of the thin metal layer is uncertain in the features at the edges of the substrate and in the high aspect ratios formed therein, thereby leading to an increase in void formation and other defects in filling substrates.
Additionally, deposited seed layers may become damaged during the plating process, and thereby form defects, which can detrimentally affect additional plating of material into the feature. For example, in conventional plating processes, a substrate is submerged into an electroplating bath and then power is applied to the substrate to deposit material thereon. However, the depositing material may dislodge portions of the seed layer, or etch portions of the seed layer, from the substrate surface, which loss of seed layer material may result in forming defects, such as discontinuities. Also, thin seed layers can be “deplated” from the substrate surface during the application of the initial pulse of pulse plating techniques, which use alternating voltages or currents to deposit and dissolve materials from a substrate surface to produce conformal depositions.
Therefore, there is a need for a method for electrochemical deposition of a metal into high aspect ratio structures on a substrate that provides void-free or seam-free fill of high aspect ratio structures. Ideally, the method for electroc
Hey Peter
Kwak Byung-Sung Leo
Applied Materials Inc.
Koehler Robert R.
Moser Patterson & Sheridan
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