Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2000-02-18
2003-11-25
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C365S104000, C365S200000, C714S710000
Reexamination Certificate
active
06654849
ABSTRACT:
TECHNICAL FIELD
The technical field is computer architectures using microcode instructions.
BACKGROUND
Current computer systems may support multiple instruction sets. For example, some computer systems may implement a reduced instruction set computing (“RISC”) architecture, but may also implement a complex instruction set computing (“CISC”) instruction set architecture (“ISA”) by emulating the CISC instructions with instructions from the RISC instruction set. The CISC instructions are referred to as macroinstructions and the RISC instructions are referred to as microinstructions.
Converting from a macroinstruction to microinstructions is often accomplished using one or more large, read-only memory (“ROM”) structures. The ROM structures contain the microinstructions needed to emulate the original macroinstruction. The read-only nature of the memory structure allows for dense packing of the data.
A mechanism may be added to the computer system that allows the ROM to be corrected, or patched, by software without having to change hardware features. The method or apparatus for doing this patch may involve providing an array of random access memory (“RAM”) that is written to by software. The RAM is significantly more costly in terms of area to implement, so that the size of the RAM is typically many times smaller than the size of the ROM.
A common method for addressing the RAM is to append the RAM address to the end of the address space to which the ROM corresponds. In many cases, this requires extra addressing bits. Moreover, because the RAM is small, the actual address space that could be included with these extra addressing bits is often only partially populated. In an example, a 4K entry ROM and a 32-entry RAM requires 12 address lines for the ROM and another address line for the 32-entry RAM.
SUMMARY
To overcome problems inherent in adding an additional address line for a patch RAM, the RAM and ROM are overlaid so that no additional address lines are needed.
The ROM structure may be a precharge-pull down or precharge-pull up structure. Other memory structures may also use the overlaid RAM/ROM configuration. Overlaying the RAM and the ROM may require that a subset of the ROM addresses be decoded and the ROM inhibited from responding. However, this can add extra timing and load to address decoders, especially when the overlapping section of RAM and ROM fall into several different ROM blocks. Accordingly, the normal ROM access is allowed to occur but the ROM is configured to be empty in all of the overlapping locations. The ROM is configured to be empty by not providing any programming field effect transistors (“FETs”) in the overlap region of the ROM. Without the programming FETs, bit lines in the overlapped region of a ROM cannot change value from the pre-charged level. In the overlap region the RAM is free to either leave the pre-charged level unchanged (usually a logical zero) or to drive the node (usually a logical one). The ROM, not having any programming FETs in the overlap region, cannot conflict with the RAM and change the desired value. Overlapping the ROM and RAM in this fashion saves an address bit without incurring increased decode burden on the ROM address bits.
In an alternative configuration, an existing ROM block may be replaced with a RAM block. This configuration also minimizes additional loading.
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patent: 6073252 (2000-06-01), Moyer et al.
Wolfe, A., “Patents shed light on Merced's Innards”, Electronic Engineering Times, Feb. 15, 1999, pp. 43-44.
Brockmann Russell C
Liao Kevin
Kim Matthew
Tran Denise
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