Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-07-24
2000-09-12
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711127, 711122, G06F 1200
Patent
active
061192023
ABSTRACT:
A method and apparatus is disclosed to improve the transfer of data from a transition cache to a level one data cache wherein the transition cache is receiving data from a plurality of data devices. In particular, logic is implemented via a line fill sequencer that allows for the interleaving of data packets being written into the level one data cache. Thus, data packets originating from a "fast" level two data cache can be interleaved with data originating from a "slow" system bus to avoid delays to the data originating from the level two data cache. Accordingly, the cache miss sequencer tracking the data from the level two data cache can be retired sooner.
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Borkenhagen John Michael
Brookhouser James Ira
Chan Eddie P.
Hoffman Michael F.
International Business Machines - Corporation
McLean Kimberly
Pitts S. Jared
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