Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Patent
1996-12-27
1998-10-13
Westin, Edward P.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
326121, 326 97, H03K 19096
Patent
active
058217754
ABSTRACT:
The present invention is an improved interface between monotonic and non-monotonic domino logic. A monotonic domino logic block is clocked by CLK. The last stage of the monotonic domino logic is clocked by the delayed clock, DCLK, to extend its evaluation period beyond Phase I by a brief window of time, t.sub.d. The true output and the inverted output of the last stage of the monotonic domino logic block are inputs to a non-monotonic domino evaluation tree. The non-monotonic domino evaluation tree operates while an evaluation control block is ON. The evaluation control block is ON only during that extension of the evaluation period, t.sub.d, for a time less than or equal to the period t.sub.d. Since the output of the last stage of the monotonic logic block remains stable during this extended evaluation period, and the non-monotonic domino evaluation tree operates at most during this window of time, there is no need to use latches or use a dual rail implementation for the monotonic logic.
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Harris David
Mehta Gaurav G.
Singh S. Deo
Intel Corporation
Le Don Phu
Westin Edward P.
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