Electrical computers and digital data processing systems: input/ – Access locking
Reexamination Certificate
2001-03-01
2003-12-16
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Access locking
C710S022000, C710S026000, C710S027000, C710S028000, C710S308000, C710S312000, C710S313000, C710S314000, C710S315000, C711S152000, C711S153000
Reexamination Certificate
active
06665759
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to an improved data processing system and, more particularly, to an improved logically partitioned data processing system. Still more particularly, the present invention relates to logically partitioning PCI I/O slots.
2. Description of Related Art
A logical partitioning (LPAR) functionality within a data processing system (platform) allows multiple copies of a single operating system (OS) or multiple heterogeneous operating systems to be simultaneously run on a single data processing system platform. A partition, within which an operating system image runs, is assigned a non-overlapping sub-set of the platform's resources. These platform allocable resources include one or more architecturally distinct processors with their interrupt management area, regions of system memory, and I/O adapter bus slots. The partition's resources are represented by the platform's firmware to the OS image.
Each distinct OS or image of an OS running within the platform are protected from each other such that software errors on one logical partition cannot affect the correct operation of any of the other partitions. This is provided by allocating a disjoint set of platform resources to be directly managed by each OS image and by providing mechanisms for ensuring that the various images cannot control any resources that have not been allocated to it. Furthermore, software errors in the control of an OS's allocated resources are prevented from affecting the resources of any other image. Thus, each image of the OS (or each different OS) directly controls a distinct set of allocatable resources within the platform.
Currently, there is no mechanism that enforces logical partitioning of direct memory access (DMA) addresses as well as other accesses involving PCI I/O slots. Therefore, it would be advantageous to have an improved method and apparatus for enforcing logical partitioning among PCI I/O slots that includes enforcement of DMA address ranges.
SUMMARY OF THE INVENTION
The present invention provides a method, system, and computer program product for enforcing logical partitioning of input/output slots within a data processing system. In one embodiment, the system includes a hypervisor and at least one DMA address checking component. The hypervisor receives non-direct-memory-access requests for access to input/output slots and prohibits devices within one logical partition from accessing the input/output slots assigned to a different logical partition. The DMA address checking component receives direct-memory-access requests and prohibits requests for addresses not within the same logical partition as the requesting device from being completed. Requests with addresses corresponding to the same logical partition as the requesting device are placed on the primary PCI bus by the DMA address checking component for delivery to the system memory.
REFERENCES:
patent: 4564903 (1986-01-01), Guyette et al.
patent: 4843541 (1989-06-01), Bean et al.
patent: 5067075 (1991-11-01), Sugano et al.
patent: 5345590 (1994-09-01), Ault et al.
patent: 5659756 (1997-08-01), Hefferon et al.
patent: 6098113 (2000-08-01), Heil et al.
patent: 6223230 (2001-04-01), Garnett et al.
patent: 6314501 (2001-11-01), Gulick et al.
IBM Technical Disclosure Bulletin, vol. 39, No. 12, Dec. 1996, “Hypervisor High Performance Synchronous Dispatch for Coupled Systems”, one page.
IBM Technical Disclosure Bulletin, vol. 38, No. 04, Apr. 1995, “VM MPG Operating as a DRF Hypervisor as a First Level Guest Under PR/SM”, p. 325.
IBM Technical Disclosure Bulletin, vol. 36, No. 03, Mar. 1993, “Sharing Read-Only Memory among Multiple Logical Partitions”, pp. 303-304.
IBM Technical Disclosure Bulletin, vol. 39, No. 12, Dec. 1996, “Highly Parallel Coupling Facility Emulator/Router with Shadowed Link Buffers”, 2 pages.
IBM Technical Disclosure Bulletin, vol. 39, No. 06, Jun. 1996, “Coordinating Multiple Server Partitions to Enter Power-Save State”, pp. 235-239.
Dawkins George John
Lee Van Hoa
Randall David Lee
Tran Kiet Anh
Gaffin Jeffrey
McBurney Mark E.
Nguyen Mike
Yee Duke W.
Yociss Lisa L. B.
LandOfFree
Method and apparatus to implement logical partitioning of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus to implement logical partitioning of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus to implement logical partitioning of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3168980