Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2007-04-03
2007-04-03
Cho, James (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S072000, C326S086000, C327S261000
Reexamination Certificate
active
11000468
ABSTRACT:
A driver includes, in part, a delay chain having disposed therein a multitude of accessible nodes, and a control logic coupled to the various nodes of the delay chain to generate the signals applied to the gate terminals of the PMOS and NMOS transistors disposed in the driver. The nodes that are accessed and tapped may or may not be the successive nodes disposed along the delay chain. Optionally four nodes of the delay chain are tapped to supply signals to the control logic. Two of the nodes, carrying in-phase signals, are tapped to generate a first signal, which is used to generate a second signal driving the NMOS transistor. The other two nodes, carrying in-phase signals, are tapped to generate a third signal, which is used to generate a fourth signal driving the PMOS transistor. The first signal is 180° out-of-phase with respect to the third signal.
REFERENCES:
patent: 5272729 (1993-12-01), Bechade et al.
patent: 5519344 (1996-05-01), Proebsting
patent: 5926050 (1999-07-01), Proebsting
patent: 6163174 (2000-12-01), Friedman et al.
patent: 6586973 (2003-07-01), Yokoyama et al.
Cho James
Crawford Jason
Exar Corporation
Townsend and Townsend / and Crew LLP
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