Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-11-13
2007-11-13
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
10045523
ABSTRACT:
A computer-implemented method includes inputting a netlist and generating symbols and connections formed according to the netlist and a selected wiring harness layout dimension. A wiring harness diagram is generated along the layout dimension according to the symbols and the connections.
REFERENCES:
patent: 6269471 (2001-07-01), Yamano et al.
patent: 6308143 (2001-10-01), Segawa
patent: 6349403 (2002-02-01), Dutta et al.
patent: 6353918 (2002-03-01), Carothers et al.
patent: 6434721 (2002-08-01), Chiluvuri et al.
patent: 6449761 (2002-09-01), Greidinger et al.
patent: 6457165 (2002-09-01), Ishikawa et al.
U.S. Appl. No. 09/771,115, filed Jan. 25, 2001, Shropshire.
“Logical Cable”, a Cabling Design & Analysis Datasheet published by Mentor Graphics, copyright © 2001.
“Capital H”, a Cabling Design & Analysis Datasheet published by Mentor Graphics, copyright © 2001.
“The One-Minute Sale: Logical Cable™” published by Mentor Graphics.
Geisler Steve
Pannala Geetha
Chiang Jack
Klarquist & Sparkman, LLP
Tat Binh
LandOfFree
Method and apparatus to generate a wiring harness layout does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus to generate a wiring harness layout, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus to generate a wiring harness layout will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3886856