Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-06-06
2004-05-11
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06735754
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to the process of laying out an integrated circuit. More specifically, the present invention relates to a method and an apparatus for global routing during layout of an integrated circuit.
2. Related Art
As rapid advances in semiconductor technology make it possible to incorporate larger amounts of circuitry onto a semiconductor chip, it is becoming increasingly harder to route signal lines between circuit components. In order to simplify the process of routing signal lines, the routing process is generally divided into a global routing operation, which is followed by a detailed routing operation. Global routing typically entails dividing the chip into rectangular tiles, mapping the connection points to the tile centers, and routing the connections over a tile adjacency graph (also called a global grid graph.) Global routing is generally much faster than detailed routing and gives valuable feedback about possible congestion problems in the design. Additionally, if routing capacities are assigned to the global tiles and the global routes are chosen to minimize the tile congestion with respect to these global capacities, the later detailed routing can be restricted to routing signals within these global routing tiles.
Typically, the global routing tiles are defined by placing imaginary vertical and horizontal cutlines across the entire layout area. The resulting checkerboard pattern describes the global routing tiles. Using fewer cutlines results in larger tiles and faster global routing, though with less accuracy in the congestion estimation and potentially more conflicts in the later detailed routing operation. Using a larger number of cutlines produces smaller tiles and leads to better routing, but takes considerably more run-time.
Different portions of the chip are designed in different ways. For datapath design, the circuits are placed in uniform width stacks. Datapath connections are typically forged within the width of the stacks to minimize congestion and electrical problems. For overall chip design, there are fewer restrictions on wiring. However, the chip size may be so large that a detailed design of the entire chip is not feasible.
In this case, the chip may be partitioned hierarchically into smaller blocks, with each block designed separately and block-to-block connections located at the boundary. However, the block boundary connections need to be assigned. Global routing may be used to assign the block boundary connections by first removing the block boundaries and performing a global routing for all nets. A given block boundary is then intersected with a given global path of a net to define a boundary connection within this intersection region for the net.
For both datapath and hierarchical wiring, it is desirable to have small tiles sizes. For datapaths, the tile width should correspond to the bit-width so that nets may be restricted to within their bit-stack. For hierarchical blocks, having smaller tiles provides tighter restrictions on the block boundary pins. However, using these smaller tile sizes to route the entire chip leads to prohibitively large run-times for global routing.
What is needed is a method and an apparatus that gives the benefit of routing with smaller tiles without the associated expense of excessive run-time.
SUMMARY
One embodiment of the present invention provides a system that facilitates generating a global routing for a layout of an integrated circuit. The system operates by first receiving a netlist to be routed. The system partitions this netlist into global signals, datapath signals, and control signals. Next, the system creates a first tiling grid of the integrated circuit and routes connection nets between tiles within the first tiling grid. The system then selects an area within the integrated circuit that includes a portion of the integrated circuit larger than a tile in the first tiling grid. The system also creates a second tiling grid of the selected area, wherein tiles of the second tiling grid are smaller than the tiles of the first tiling grid. Next, the system routes connection nets within the selected area. During this process, connection nets are routed between tiles on the second tiling grid while routings within the first tiling grid are maintained. Finally, the system merges connection nets within the first tiling grid with connection nets within the second tiling grid to form the global routing.
In one embodiment of the present invention, the system assigns boundary connections between the first tiling grid and the second tiling grid.
In one embodiment of the present invention, tiles of the first tiling grid are rectangular.
In one embodiment of the present invention, tiles of the second tiling grid are rectangular.
In one embodiment of the present invention, the selected area includes a datapath, and the second tiling grid tile on the datapath is one bit wide.
In one embodiment of the present invention, the area includes a control signal area, and the second tiling grid tile on the control signal area is assigned a specified size.
In one embodiment of the present invention, selecting the area includes selecting a set of areas where each area in the set of areas is routed separately.
In one embodiment of the present invention, the method involves routing connection nets that pass through the selected area without connecting within the selected area while routing other connection nets within the area.
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Mehrotra Sharad
Patel Parsotam T.
Grundler Edward J.
Park Vaughan & Fleming LLP
Siek Vuthe
Sun Microsystems Inc.
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