Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2005-06-06
2011-11-08
Richards, N Drew (Department: 2895)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S414000
Reexamination Certificate
active
08053774
ABSTRACT:
A wafer having a plurality of dies (also called array chips) on the wafer, the die having an electrode to generate a deprotecting reagent, a working electrode to electrochemically synthesize a material, a confinement electrode adjacent to the working electrode to confine reactive reagents, and a die pad, wherein die pads of the plurality of dies are interconnected on the wafer to electrochemically synthesize the material in parallel on a plurality of working electrodes is disclosed. Also, a method for wafer-scale manufacturing of a plurality of dies and a method for electrochemically synthesizing a material in parallel on a plurality of dies on a wafer are disclosed.
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Chinese Office Action with English translation dated Jun. 23, 2011, 4 pages.
Barnett Brandon
Dubin Valery M.
Gstrein Florian
Holt Gordon D.
Intel Corporation
Lee Jae
Pillsbury Winthrop Shaw & Pittman LLP
Richards N Drew
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