Computer graphics processing and selective visual display system – Computer graphics display memory system – Graphic display memory controller
Reexamination Certificate
1999-12-16
2003-07-15
Tung, Kee M. (Department: 2676)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Graphic display memory controller
C345S213000, C711S106000, C365S222000
Reexamination Certificate
active
06593930
ABSTRACT:
FIELD OF THE INVENTION
The present invention provides a method and apparatus to control a memory maintenance operation. More particularly, the initiation of a memory maintenance operation is controlled to provide for execution of the memory maintenance operation during a screen blanking event.
BACKGROUND OF THE INVENTION
In known electronic systems, memory maintenance operations must be performed within set intervals of time. If memory maintenance operations are not performed within a specified period of time, memory data can be lost, memory performance can become degraded, etc. Known methods and apparatus to control the execution of memory maintenance operations include the use of a timer (e.g., a counter that counts a clock signal) to initiate a memory maintenance operation. The timer can generate a memory maintenance enable signal that initiates the execution of the memory maintenance operation. The timer generates the memory maintenance enable signal at least once within a set period of time (e.g., at least every 15 microseconds).
In a computer system that uses Rambus® memory, operation of the Rambus® memory system has memory maintenance operations that cause the memory to shut down and not serve memory requests for periods of time. Rambus® technology is licensed by Rambus Inc. of Mountain View, Calif. Rambus® memory maintenance operations include memory controller temperature calibration, memory device temperature calibration, memory controller current calibration, memory device current calibration, DLL (Dynamic Link Layer) refresh for device in Nap mode, memory refresh, etc. Rambus® memory maintenance operations can occur relatively infrequently. In known Rambus® implementations, certain memory maintenance operations may occur every 100 milliseconds and have durations of up to 2.5 microseconds.
During Rambus® memory maintenance operations, the Rambus® memory is shut down with respect to reading and writing data to the Rambus® memory. In other words, the Rambus® memory does not service memory requests during memory maintenance operations. As used to describe embodiments of the present invention, a memory maintenance operation encompasses a memory operation during which the memory does not service memory request (e.g., memory reads, memory writes, etc.). In systems servicing high-bandwidth, real-time data streams (e.g., displaying video data, capturing video data, processing cable television transmissions, etc.), a known method of addressing memory service shutdowns is to utilize memory buffers. During memory shutdowns, a memory buffer can receive data written to the memory. Data can also be read from a memory buffer during a memory shutdown. Typically, the size of a buffer is based at least on the worst-case period of memory service shutdown and the memory bandwidth required by devices and/or applications writing data to, and reading data from, memory.
The use of a buffer to service memory requests during a memory shutdown consumes silicon area resources. For example, a buffer can be implemented as a dedicated portion of a processor, as a dedicated portion of a Rambus® controller, etc. Buffer operations (e.g., keeping a read buffer sufficiently full, keeping a write buffer sufficiently empty, etc.) can disadvantageously affect system performance by generating high-priority requests to write data to, or read data from, the buffer.
In view of the foregoing, it can be appreciated that a substantial need exists for a method and apparatus which can control the initiation of memory maintenance operations in an efficient and effective manner.
SUMMARY OF THE INVENTION
For one embodiment of the present invention, a memory controller can initiate the execution of a memory maintenance operation based at least in part on a first signal from a screen blanking event counter. A memory maintenance state circuit can be coupled to the screen blanking event counter to receive the first signal. The memory maintenance state circuit can output a memory maintenance enable signal to initiate the execution of the memory maintenance operation.
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Kahn Opher D.
Sheaffer Gad S.
Intel Corporation
Kenyon & Kenyon
Tung Kee M.
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