Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2002-01-10
2004-06-08
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S760020
Reexamination Certificate
active
06747471
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates methods and structures for evaluating and assuring reliability of electronic components. More particularly this invention relates to testing methods and structures to evaluate and minimize burn-in testing of semiconductor wafers onto which integrated circuits are formed.
2. Description of Related Art
As integrated circuit densities and circuit performance has increased, the equipment necessary to evaluate and assure the reliability and functionality of the integrated circuits has become more complex and consequently more expensive. It is well known in the art and shown in
FIG. 1
that the hazard rate or probability of failure of integrated circuits follows the commonly referred to “bathtub” curve
10
. During evaluation of product requirements, the target hazard rate
5
of the integrated circuit is established. Whenever the hazard rate
10
of the integrated circuit exceeds the target hazard rate
5
, the integrated circuit is not deemed sufficiently reliable for its intended application. The failures that occur in the early life period
15
of operation of the integrated circuit are referred to as infant mortality.
To predict the actual hazard rate
10
of the integrated circuits, wafer level reliability experiments are performed to detect the failure mechanisms and their impact on the actual hazard rate
10
. The predicted hazard rate
20
does not detect lot-to-lot variations that impact the hazard rate
10
nor does it detect and unique variations
25
in the actual hazard rate
10
. The reliability experiments facilitate determination of a burn-in schedule that is to eliminate the infant mortality failures from the integrated circuits. However, the lot-to-lot variations may mean that the burn-in schedule may significantly shorten the useful duration
30
of the integrated circuits and in the extreme, cause the integrated circuit to enter the wear-out period
35
earlier than expected.
The reliability evaluation testing and the burn-in testing utilize unique integrated circuit structures to evaluate the results of stress upon the integrated circuit that can cause failure. Typically the structures include, capacitor dielectric film evaluation devices, gate oxide integrity devices, polycrystalline silicon heating devices, contact metallurgy evaluation chains, interlayer via chains, MOS evaluation devices, plasma etching antenna effect patterns, metal electromigration structures, memory cell array, and specially designed circuit block structures. These structures examine the susceptibility of the integrated circuit failures due to such failure mechanisms as pin holes in insulating material such as gate oxides and other inter-level insulating materials, corrosion of metal layers in the presence of moisture, electromigration of the metal layers, etc.
During the technology reliability evaluation the test structures are formed as test sites on an integrated circuit die. An integrated circuit die typically contains one unique test structure to allow creation of a sufficiently large sample size to detect long term or low-level failure phenomena. However, during wafer-level test, the actual functional integrated circuits occupy, as shown in
FIG. 2
, the die
50
and any test structures or test sites are placed in the kerf or scribe lines
55
area between each integrated circuit die
50
. Since the scribe line area
55
is relatively small, the test structure must occupy a relatively small area. This forces a relatively small sample size for evaluation of particular failure mechanisms that have low defect density. Thus, this small sample size does not allow sufficient sensitivity to indicate the defect density prior to burn-in. This forces the burn-in to be longer than necessary to assure that the infant mortality failures are screened from the production lot. For instance, evaluation of the characteristics of individual MOS transistors requires four bonding pads for each device. The bonding pads are relatively large and consume significantly more area than the MOS transistors. Therefore placing test structures for the individual transistors in the scribe lines
55
limits the number of transistors available for evaluation.
U.S. Pat. No. 6,157,046 (Corbett et al.) describes a semiconductor test chip. The semiconductor test chip includes structures for evaluating bond pad design effects and damage (cratering) effects, scribe lane width effects, thermal impedance effects of the die, ion mobility evaluation capabilities, and flip chip on board application test capabilities.
U.S. Pat. No. 6,064,213 (Khandros et al.) describes a wafer-level burn-in and test system that allows a wafer containing integrated circuits to be stressed and evaluated to conduct burn-in of the wafer to assure correct functioning of the wafer.
U.S. Pat. No. 6,246,075 (Su et al.) describes an ensemble of test structures for monitoring gate oxide defect densities and plasma antenna effects. The structures maybe included as a test site on a wafer containing integrated circuits or as test structures for reliability evaluation of an integrated circuit process.
U.S. Pat. No. 5,981,971 (Miyakawa) describes a semiconductor ROM wafer test structure, and IC card. The circuit structure such as the ROM is tested via a test pad formed on a scribe line. Since the test pad is formed on the scribe line, when the die containing the ROM has been cut off and separated from other chips along the scribe lines, the test pads are destroyed preventing future testing of the ROM.
U.S. Pat. No. 5,946,248 (Chien et al.) and U.S. Pat. No. 5,995,428 (Chien et al.) describe methods where a wafer containing memory devices, such as a DRAM (dynamic random access memory) are subjected to a burn-in operation of the memory device. As described in Miyakawa, pads are formed in the scribe lines. These pads are used to transfer an externally generated burn-in enable signal and a DC bias voltage to each memory device. Since the pads for burn-in wiring are formed in the scribe lines, they will not take additional space on the die where each memory device is formed.
U.S. Pat. No. 5,057,441 (Gutt et al.) describes a method for reliability testing integrated circuit metal films using a noise measurement technique. In one embodiment, a film portion to be tested is incorporated in a Wheatstone bridge circuit within a test site. A relatively large direct current is passed through the film to stimulate 1/f
2
noise. A relatively small alternating current is concurrently passed through the film. The bridge imbalance signal at the ac frequency is amplified and demodulated by a phase-locked amplifier, and is then frequency analyzed. The film is evaluated by comparing the resulting noise power spectrum with predetermined standards.
U.S. Pat. No. 5,808,947 (McClure) teaches an integrated circuit that includes both a wafer test-mode path that is operable to carry a wafer test-mode signal and a wafer power-supply path that is operable to carry a wafer power-supply signal. The integrated circuit includes functional circuitry that supports normal and wafer-test modes of operation and that is coupled to the wafer test-mode path before the die is detached from the wafer. The functional circuitry is tested for operation when placed in the wafer test mode and functions normally when removed from the wafer test mode. The circuitry for the wafer test-mode path and the wafer power-supply path are located in the scribe line region of the wafer.
U.S. Pat. No. 6,233,184 (Barth et al.) describes structures for wafer level test and burn-in. The structures include a state machine or programmable test engines located on the wafer in the area not including the functional circuitry. Each test engine requires fewer than ten connections and each test engine can be connected to multiple integrated circuit die. Thus, the number of pads of the wafer that must be connected for test is substantially reduced while a large degree of parallel testing is still provided. Connections to the wafer and between te
Chen Kuo-Tso
Liu Chi-Ming
Ackerman Stephen B.
Cuneo Kamand
Knowles Billy
Nguyen Tung X.
Saile George O.
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