Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-04-15
2008-04-15
Sough, Hyung S. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S142000, C711S134000, C711S144000, C711S145000, C711S146000
Reexamination Certificate
active
07360031
ABSTRACT:
Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces. The apparatus includes an arbitration unit, a host interface unit, and a memory interface unit. The arbitration unit provides an interface to one or more I/O agents that issue atomic transactions to access and/or modify data stored in a shared memory space accessed via the memory interface unit. The host interface unit interfaces to a front-side bus (FSB) to which one or more processors may be coupled. In response to an atomic transaction issued by an I/O agent, the transaction is forked into two interdependent processes. Under one process, an inbound write transaction is injected into the host interface unit, which then drives the FSB to cause the processor(s) to perform a cache snoop. At the same time, an inbound read transaction is injected into the memory interface unit, which retrieves a copy of the data from the shared memory space. If the cache snoop identifies a modified cache line, a copy of that cache line is returned to the I/O agent; otherwise, the copy of the data retrieved from the shared memory space is returned.
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Cabot Mason B.
Lakshmanamurthy Sridhar
Nanavati Sameer
Rosenbluth Mark
Ahmed Hamdy S
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Sough Hyung S.
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