Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2000-12-18
2004-04-06
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S794000, C714S795000, C714S792000, C375S262000, C375S263000, C375S341000
Reexamination Certificate
active
06718511
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an apparatus for detecting a signal received from a channel signal and for transforming this signal into a binary code sequence. More particularly the invention refers to a signal processing apparatus, which can perform a maximum likelihood detection of the reproduced data from an optical disk.
BACKGROUND OF THE INVENTION
The idealized recording channel has a low pass nature, just as the Duobinary (1+D) partial response (PR1 class) and therefore, for detecting the data read from an optical disk the (1+D) partial response signaling technique can be used.
A method and the respective hardware architecture for implementing a known method requires many computations, particularly for branch metrics calculations and for difference path metric calculations, that requires the additional time and leads to decrease the performance of the detector.
In a known maximum likelihood detector, also referred to herein as ML detector or as MLD apparatus, has been implemented a method, which is also called “Viterbi Detection”. This Method is based on the assumption, that the recording channel has a precoder. This method is extremely sensitive to the input signal amplitude variations, because a large number of threshold conditions, for example comparers are used.
SUMMARY OF THE INVENTION
An object of the invention is to develop a maximum likelihood detector with minimal hardware complexity, maximum computational speed, which maximum likelihood detector is not sensitive to variations in the input signal amplitude. In order to reach this goal the following principles are used.
The so-called maximum likelihood detection boils down to finding the admissible sequence x=x
0
, x
1
, . . . , x
n
that is closest to the detector input sequence B=B
0
, B
1
, . . . , B
n
in the Euclidean sense. The Euclidean distance &lgr; between detector input B and admissible sequence x is
λ
=
∑
k
=
0
n
(
B
k
-
x
k
)
2
(
1
)
This is a sum of so-called branch metrics b
k
wherein:
b
k
(
B
k
−x
k
)
2
(2)
All metrics b
k
may be computed as soon as the k
th
detector input B
k
becomes available. The detector must determine the path through the trellis for which the sum of all branch metrics is smallest. In
FIG. 5
there is shown an example of a state transition diagram for two states 0 and 1, which are also indicated as p and m, respectively. The different transitions are indicated by b_pp, b_mp, b_pm, and b_mm, wherein the first index indicates the actual state while the second index indicates the previous state.
For a two state (1+D) maximum likelihood detection the branch metrics are:
1. The data transition path from 1 to 0 in the state transition diagram
b
—
mp=
(
B
k
+Am
)
2
; (3)
2. The data transition path from 0 to 1 in the state transition diagram
b
—
pm=
(
B
k
−Am
)
2
; (4)
3. The data transition path from 0 to 0 in the state transition diagram
b
—
mm=
(
B
k
+2*
Am
)
2
; (5)
4. The data transition path from 1 to 1 in the state transition diagram
b
—
pp=
(
B
k
−2*
Am
)
2
; (6)
wherein the MLD has as input the output of the (1+D) equalizer,
B
k
=A
k
+A
k−1
, (7)
where
A
k
=Y
k
−Am
, (8)
and wherein Y
k
is a sampled value of an HF signal read from a recording medium after analog-to-digital conversion and Am is a reference value, especially a current value of a so-called slicer.
FIG. 1
shows the signals Y
k
, A
k
, B
k
respectively. The time axis kT is subdivided in equidistant parts, each vertical line indicating a k-th point in time at which a sample, indicated by a dot, is taken from the continuous signal. The four branch metrics b_mp, b_pm, b_mm, b_pp are calculated at the same time in each decision point (k). One can see that the branch metrics values are the absolute values, which are always positive. This is caused by the square operation. The absolute values undergo the operation
b
—
ml=MIN
(
b
—
mp, b
—
pm, b
—
pp, b
—
mm
), (9)
where b_ml is the value that corresponds to the at most smallest branch metric. b_ml is thus the branch metric having maximum likelihood of corresponding to the correct transition. Later the value b_ml is used for a merge determination operation.
It is an object of the invention to propose a maximum likelihood detector having reduced complexity.
In order to increase the performance of the maximum likelihood detector, also referred to herein as ML detector or as MLD, without loss of the detecting ability, and in order to reduce the hardware complexity some modifications are implemented into the branch metrics calculation block and the different path metric calculation block is deleted according to the invention.
According to the invention the above-mentioned computations are simplified as follows:
First the square performance operation is rejected. This has the advantage to reduce complexity of the maximum likelihood detector. In the example described above four multiplication operations are avoided.
Second the branch metrics for non-changing state are not determined. This does not influence the maximum likelihood detection in a negative way as nearly no such transitions happen because the HF signal shape is not flat. This property makes possible to reject the branch metric computations (5) and (6).
Further, the branch metrics are calculated by using some properties of the arithmetic system of hardware. This procedure will be described in more detail below.
Minimum branch metrics are determined by computing a sum of absolute values of two branch metrics and using the sign of this sum for determining the minimum branch metrics. This sign is e.g. indicated by the most significant bit in the two's complement binary notation or in any other way, depending on the kind of notation used, known to the skilled person. Advantage of this feature is that summation operation and determination of the sign of a variable are operations which are easy to implement and quickly to perform.
Preferably, the absolute value to be input to the adding operation is generated differently for different branch metrics. For a first branch metric the most significant bit is checked. If it is set to “low” level, the remaining less significant bits, which correspond to the absolute level, are also taken as absolute level for the summation. If the most significant bit is set to “high” level, then the inverted less sigificant bits are taken as absolute value for the summation. For a second branch metric, the selection is done in the opposite way. In this case the absolute value is taken unchanged if the most significant bit is set to “high” level, and its inverted value is taken else. This is true for the two's complement binary notation, however, similar evaluation of the sign, which here corresponds to the most significant bit, and transformation of the absolute value can easily be performed by a skilled person using a different notation than the two's complement notation.
According to the invention, the type of merge is detected from two successive minima of the generated branch metrics. This allows to determine the type of merge even if not all possible types of branch metrics are generated. The types of merges in case of two states are: Change of state from “high” to “low”; change of state from “low” to “high”; and no change of state. In case that branch metrics are generated only for “change of state” then a change of state is determined only if the type of two successive minimum branch metrics changes. No change of state is determined if successive minimum branch metrics are identical.
The device according to the invention comprises the elements as indicated in the independent device claim. An advantage of this device is its relatively easy construction without need of complex or space consuming elements. The equalizer preferably is a (1+D) linear equalizer, combining two successive input values,
Kabutz Marten
Kravtchenko Alexander
Peytavin Bruno
Kiel Paul P.
Lamarre Guy J.
Thomson Licensing S.A.
Tripoli Joseph S.
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