Method and apparatus to data log at-speed March C+ memory BIST

Details Method and apparatus to data log at-speed March C+ memory BIST Method and apparatus to data log at-speed March C+ memory BIST

2005-09-13

2005-09-13

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

Reexamination Certificate

active

06944806

ABSTRACT:
A method and apparatus for data logging at-speed March C+ memory Built-in Self-tests. The method of testing a memory includes providing the memory with a Test Control and Observe wrapper; enabling a Built-in Self-test mode operation; utilizing the Test Control and Observe wrapper to capture a memory output; and holding a memory data when a failure occurs. The apparatus includes a processing unit; a Built-in Self-test controller coupled to the processing unit; a data circuit coupled to the Built-in Self-test controller; an address circuit coupled to the Built-in Self-test controller; a control circuit coupled to the Built-in Self-test controller; a memory coupled to the data circuit, the address circuit and the control circuit; a comparator circuit coupled to the memory and to the Built-in Self-test controller; and a memory Test Control and Observe wrapper coupled to the memory.

REFERENCES:
patent: 6691264 (2004-02-01), Huang

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