Method and apparatus to create bypass logic in a digital...

Details Method and apparatus to create bypass logic in a digital... Method and apparatus to create bypass logic in a digital...

2007-11-20

2007-11-20

Whitmore, Stacy (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

10606868

ABSTRACT:
A method and apparatus to create bypass logic in a digital circuit design comprising coupling a first latency delay unit to a data input of the conditional state element (e.g., a flip-flop). Coupling a second latency delay unit to an enable input of the conditional state element. Coupling a first input of a multiplexer to an output of the conditional state element. Coupling a second input of the multiplexer to the data input of the conditional state element; and coupling a select line of the multiplexer to the enable input of the conditional state element to form a logically redundant element. Replacing the conditional state element in a feedback loop of a finite state machine with the logically redundant element and manipulating latency delay units to create bypass logic in the digital circuit design.

REFERENCES:
patent: 5301153 (1994-04-01), Johnson
patent: 6212629 (2001-04-01), McFarland et al.
patent: 6219819 (2001-04-01), Vashi et al.
patent: 6625788 (2003-09-01), Vashi et al.

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