Method and apparatus to control memory accesses

Details Method and apparatus to control memory accesses Method and apparatus to control memory accesses

2002-02-21

2004-09-28

Bragdon, Reginald G. (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

Reexamination Certificate

active

06799257

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to the field of electronics. In particular, the present invention is related to a method and apparatus for controlling memory accesses.
2. Description of the Related Art
Dynamic Random Access Memories (DRAMs) have memory precharge, activate, read, and write operations. In particular, a memory controller that addresses a bank of memory must first precharge the memory bank, then the addressed page within the bank must be activated before the addressed column in that page is accessed (read or written). A “DRAM page open” or a “page hit” indicates the memory being accessed has already been precharged and activated, and data may be read or written from the page without having to precharge or activate the memory during each memory access. When a “page miss occurs” (i.e., data is accessed from a page in memory other than from the page that is open), the open page must be written back to the DRAM chip from the sense amps. Next, the new memory page has to first be precharged and activated before being accessed. Writing the old page to DRAM, and precharging and activating the new DRAM pages takes time and slows down memory accesses resulting in an inefficient use of the memory bus (reduced bandwidth) and a loss in performance of an apparatus (e.g., a computer) employing DRAM.
FIG. 1
illustrates a front side bus (FSB) controller that schedules memory accesses according to a prior art embodiment. As illustrated in
FIG. 1
, the FSB controller
105
includes a FSB scheduler
125
that schedules accesses (reads and writes) from a processor
110
to DRAM
120
via a FSB access queue
130
. The FSB controller is coupled to processor
110
via a L2 miss request bus and to memory controller
115
via a front side bus. The memory controller
115
is coupled to DRAM
120
via a memory bus. Processor
110
comprises an out-of-order core
135
and a hardware prefetcher (HWP)
140
. The out-of-order core
135
uses a pipelining technique wherein multiple instructions are overlapped in execution in an effort to improve the overall performance of the processor. The HWP prefetches data needed by execution units in the out-of-order core from DRAM.
The FSB controller
105
and in particular the FSB scheduler
125
schedules DRAM accesses from the processor
110
(i.e., from the out-of-order core and from the HWP) based upon the relative age of the instructions that caused the access (i.e., a load or store resulting in a request for reading or writing data to DRAM). Hence the accesses in the FSB access queue
130
are scheduled to DRAM in program order. In particular, DRAM accesses from the out-of-order core have priority over DRAM accesses from the HWP, and accesses generated by the out-of-order core are scheduled in program order. Thus, the FSB controller minimizes the DRAM access latency by first scheduling the accesses associated with the oldest instruction in the FSB access queue. However, scheduling DRAM accesses based upon minimizing the latency of DRAM accesses is not always the optimum solution, as successive DRAM accesses may not always access open DRAM pages. Accesses from a closed DRAM page involve writing the currently open page to DRAM, and precharging and activating a new DRAM page. Thus, accessing a closed DRAM page takes time and slows down memory accesses, thereby rendering the processor's DRAM bus inefficient.


REFERENCES:
patent: 5745913 (1998-04-01), Pattin et al.
patent: 5860106 (1999-01-01), Domen et al.
patent: 5926828 (1999-07-01), Khandekar
patent: 5966544 (1999-10-01), Sager
patent: 6026465 (2000-02-01), Mills et al.
patent: 6055650 (2000-04-01), Christie
patent: 6088772 (2000-07-01), Harriman et al.
patent: 6094717 (2000-07-01), Merchant et al.
patent: 6148380 (2000-11-01), Dodd et al.
patent: 6163838 (2000-12-01), Merchant et al.
patent: 6182177 (2001-01-01), Harriman
patent: 6212598 (2001-04-01), Jeddeloh
patent: 6212626 (2001-04-01), Merchant et al.
patent: 6243768 (2001-06-01), Khandekar
patent: 6304953 (2001-10-01), Henstrom et al.
patent: 6484239 (2002-11-01), Hill et al.
patent: 2002/0023197 (2002-02-01), Miura et al.
PCT Search Report mailed Jun. 27, 2003, Intenational Application No. PCT/US 03/02169 (6 pages).
PCT Written Opinion mailed Nov. 19, 2003, International Application No. PCT/US03/02169, 8 pages.

Affiliated with

Also associated with

Rating

Method and apparatus to control memory accesses does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus to control memory accesses, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus to control memory accesses will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3247755