Method and apparatus to calibrate DRAM on resistance (Ron)...

Details Method and apparatus to calibrate DRAM on resistance (Ron)... Method and apparatus to calibrate DRAM on resistance (Ron)...

2005-06-30

2008-10-07

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S056000

Reexamination Certificate

active

07432731

ABSTRACT:
An embodiment may comprise memory with a memory array, a resistor coupled to a reference voltage, on die termination circuitry coupled with the resistor, and an input coupled to the on die termination circuitry and coupled with the memory array, the input to receive a calibration command to stop use of the input and the memory array and calibrate the on die termination circuitry with the resistor coupled to the reference voltage. Other embodiments are disclosed herein.

REFERENCES:
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patent: 6343352 (2002-01-01), Davis et al.
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patent: 7176711 (2007-02-01), Park et al.
patent: 2004/0189343 (2004-09-01), Jang
patent: 2005/0144372 (2005-06-01), Walker
patent: 2006/0053243 (2006-03-01), David et al.
patent: 2006/0092715 (2006-05-01), Braun et al.

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