Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2005-12-30
2008-07-01
Trimmings, John P (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S005110, C714S014000, C714S031000, C714S042000, C714S047300, C714S054000, C714S704000, C714S706000, C714S715000, C714S718000, C714S719000, C714S723000, C714S724000, C714S733000, C714S734000, C702S060000, C702S099000, C365S185270, C365S201000, C365S211000, C365S227000, C365S228000
Reexamination Certificate
active
07395466
ABSTRACT:
According to embodiments of the present invention, an integrated circuit such as a processor includes a counter to count an actual number of unreliable storage locations in the processor cache, at least one register to store an acceptable number of unreliable storage locations for the cache, a detector to measure a thermal environment of the processor, and circuitry to raise an operating voltage of the processor if the actual number of unreliable storage locations exceeds the acceptable number of unreliable storage locations, and if the thermal environment is acceptable.
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Poellabauer et al., “Feedback-Based Dynamic Voltage and Frequency Scaling for Memory-Bound Real-Time Applications”, IEEE 10.1109/RTAS.2005.23, Mar. 10, 2005, pp. 234-243.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Trimmings John P
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