Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-09-19
2006-09-19
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07111270
ABSTRACT:
A method and apparatus to adaptively validate a physical net routing topology of a substrate design to a target topology of the substrate design. A tree data structure is generated by mapping physical net routing topology objects to tree data structure objects the tree data structure representing the substrate design. The tree data structure is then compressed to form a compressed tree data structure. The compressed tree data structure is validated by comparing the target topology with the compressed tree data structure to determine if the target topology is electrically equivalent to the compressed tree data structure. One or more branches of the validated tree data structure is named, and the validated tree data structure is partitioned and saved.
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McRonald Andrew J.
Meyer Neal G.
Neal Brett A.
Garbowski Leigh M.
Intel Corporation
Schwegman Lundberg Woessner & Kluth P.A.
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