Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2005-03-22
2005-03-22
Baderman, Scott (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S028000, C714S030000, C712S227000
Reexamination Certificate
active
06871298
ABSTRACT:
A dynamic test generation method and apparatus enabling verification of the parallel instruction execution capabilities of VLIW processor systems is described. The test generator includes a user preference queue, a rules table, plurality of resource-related data structures, an instruction packer, and an instruction generator and simulator. The present invention generates a test by selecting instructions for parallel execution based upon resource availability as indicated by the resource-related data structures and the processor's instruction grouping rules, simulating the parallel execution of the instructions on a golden model, updating the resource-related data structures, and evaluating the updated architectural state of the golden model.
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Cavanaugh Becky
Gowin, Jr. Robert Douglas
Hennenhoefer Eric T.
Baderman Scott
Baker & Botts L.L.P.
Damiano Anne L.
Obsidian Software, Inc.
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