Electrical computers and digital processing systems: processing – Processing control – Processing sequence control
Reexamination Certificate
2006-12-12
2006-12-12
Chan, Eddie (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Processing sequence control
Reexamination Certificate
active
07149883
ABSTRACT:
A buffer mechanism for buffering microinstructions between a trace cache and an allocator performs a compacting operation by overwriting entries within a queue, known not to store valid instructions or data, with valid instructions or data. Following a write operation to a queue included within the buffer mechanism, pointer logic determines whether the entries to which instructions or data have been written include the valid data or instructions. If an entry is shown to be invalid, the write pointer is not advanced past the relevant entry. In this way, an immediately following write operation will overwrite the invalid data or instruction with data or instruction. The overwriting instruction or data will again be subject to scrutiny (e.g., a qualitative determination) to determine whether it is valid or invalid, and will only be retained within the queue if valid.
REFERENCES:
patent: 4682284 (1987-07-01), Schrofer
patent: 4841476 (1989-06-01), Mitchell et al.
patent: 5954815 (1999-09-01), Joshi et al.
patent: 6014742 (2000-01-01), Krick et al.
patent: 6094729 (2000-07-01), Mann
patent: 6237074 (2001-05-01), Phillips et al.
patent: 6477562 (2002-11-01), Nemirovsky et al.
patent: 6704856 (2004-03-01), Farrell et al.
patent: 0458305 (1991-11-01), None
patent: 0690373 (1996-01-01), None
patent: WO 93/01545 (1993-01-01), None
patent: WO 93/17385 (1993-09-01), None
patent: WO 96/37829 (1996-11-01), None
patent: WO 96/37831 (1996-11-01), None
Graf, Rudolf F. Modern Dictionary of Electronics. 1984. Howard W. Sams and Company. Sixth Edition. p. 620.
“A 100-MHZ Macropiplined Vax Microprocessor”, Roy W. Bandeau, et al.,IEEE Journal of Solid-State Circuits, Nov. 1, 1992, vol. 27, No. 11, pp. 1589-1596.
“Optimization of Instruction Fetch Mechanism for High Issue Rates”, Thomas M. Conte, et al.,Proceedings of the Annual Synmposium on Computer Architecture, Jun. 22, 1995, vol. SYMP 22, pp. 333-344.
Search Report PCT/US 01/08104, Aug. 30, 2001.
Written Opinion-PCT/US01/08104, Feb. 4, 2002.
Hammarlund Per
Krick Robert
Blakely , Sokoloff, Taylor & Zafman LLP
Chan Eddie
Huisman David J.
Intel Corporation
LandOfFree
Method and apparatus selectively to advance a write pointer... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus selectively to advance a write pointer..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus selectively to advance a write pointer... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3718128