Method and apparatus providing non level one information...

Details Method and apparatus providing non level one information... Method and apparatus providing non level one information...

2006-07-04

2006-07-04

Vital, Pierre (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S134000, C711S137000, C711S141000, C711S144000, C711S145000, C711S146000, C711S160000

Reexamination Certificate

active

07073030

ABSTRACT:
A method and apparatus for increasing the processing speed of processors and increasing the data hit ratio is disclosed herein. The method increases the processing speed by providing a non-L1 instruction caching that uses prefetch to increase the hit ratio. Cache lines in a cache set are buffered, wherein the cache lines have a parameter indicating data selection characteristics associated with each buffered cache line. Then which buffered cache lines to cast out and/or invalidate is determined based upon the parameter indicating data selection characteristics.

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