Method and apparatus on (110) surfaces of silicon structures...

Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With specified crystal plane or axis

Reexamination Certificate

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C257S627000, C257S521000, C257S527000

Reexamination Certificate

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06960821

ABSTRACT:
Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.

REFERENCES:
patent: 3999282 (1976-12-01), Ono et al.
patent: 4466178 (1984-08-01), Soclof
patent: 4651188 (1987-03-01), Hayashi et al.
patent: 4667215 (1987-05-01), Kawamura et al.
patent: 4768076 (1988-08-01), Aoki et al.
patent: 4833516 (1989-05-01), Hwang et al.
patent: 4857986 (1989-08-01), Kinugawa
patent: 5082795 (1992-01-01), Temple
patent: 5192680 (1993-03-01), Naruse et al.
patent: 5196722 (1993-03-01), Bergendahl et al.
patent: 5364810 (1994-11-01), Kosa et al.
patent: 5371383 (1994-12-01), Miyata et al.
patent: 5583368 (1996-12-01), Kenney
patent: 5801089 (1998-09-01), Kenney
patent: 5883012 (1999-03-01), Chiou et al.
patent: 5888880 (1999-03-01), Gardner et al.
patent: 5904543 (1999-05-01), Wang
patent: 5907170 (1999-05-01), Forbes et al.
patent: 5991225 (1999-11-01), Forbes et al.
patent: 6015737 (2000-01-01), Tokura et al.
patent: 6066869 (2000-05-01), Noble et al.
patent: 6072209 (2000-06-01), Noble et al.
patent: 6097065 (2000-08-01), Forbes et al.
patent: 6255684 (2001-07-01), Roesner et al.
patent: 6320215 (2001-11-01), Bronner et al.
patent: 6358867 (2002-03-01), Tews et al.
patent: 6362494 (2002-03-01), Yagi
patent: 6383871 (2002-05-01), Noble et al.
Balk, P., “Orientation Dependence of Built-In Surface Charge on Thermally Oxidized Silicon”,IEEE, 53, (1965), pp. 2133-2134.
Carr, W. N., et al.,In:MOS/LSI Design and Application, McGraw-Hill Book Company, New York,(1972),pp. 37, 49-52.
Crowder, S. , et al., “Trade-offs in the Integration of High Performance Devices with Trench Capacitor DRAM”,Dig. Int. Electron Devices Meeting, Washington, D.C.,(Dec. 1997),pp. 45-48.
Deal, B. E., et al., “Charateristics of the Surfac -State Charge (Q) of Thermally Oxidized Silicon”,J. Electrochem. Soc.: Solid State Science, (1967),pp. 266-274.
Hodges, D. A., et al.,In: Analysis and Design of Digital Integrated Circuits, Second Edition, McGraw-Hill, Inc., New York,(1988),p. 342-344.
Irene, E. A., “The Effects of Trace Amounts of Water on the Thermal Oxidation of Silicon in Oxygen”,Journal of the Electrochemical Society: Solid-State Science and Technology, (1974),pp. 1613-1616.
Kim, Han-Soo , et al., “The 600V Rating n-ch Trench IGBT with the Low Leakage Current and the High Channel Mobility Using the (101) Oriented Trench Sidewall”,IEEE, Document No. 0-7803-3993-2/97,(1997),265-268.
King, Y. , et al., “Sub-5nm Multiple-Thickness Gate Oxide Technology Using Oxygen Implantation”,IEDM Technical Digest, (1998),pp. 585-588.
Liu, C. T., et al., “Multiple Gate Oxide Thickness for 2GHz System-on-A-Chip Technologies”,IEDM Technical Digest, (1998),pp. 589-592.
Petti, C. J., et al., “Characterization of Surface Mobility on the Sidewalls of Dry-Etched Trenches”,IEEE IEDM '88, (1988),104-107.
Sato, T. , et al., “Drift-Velocity Saturation of Holes in Si Inversion Layers”,J. Phys. Soc. Japan, 31(6), (1971),p. 1846.
Shenai, K. , “A 55-V, 0.2-microohm-cm2 Vertical Trench Power MOSFET”,IEEE Electron Device Letters, 12, (Mar., 1991),108-110.
Shenai, K. , “Electron Mobilities in MOS Channels Formed Along Anistropically Dry Etched <110> Silicon Trench Sidewalls”,Electronics Letters, 27, (Apr. 25, 1991),715-717.
Theil, J. A., “Deep Trench Fabrication by Si (110) Orientation Dependent Etching”,Journal of Vaccuum Science&Technology B: Microelectronics and Nanometer Structures, Abstract, obtained from http://ojps.aip.org/>,(Sep., 1995), 1 p.
Togo, M. , et al., “Multiple-Thickness Gate Oxide and Dual-Gate Technologies for High Performance Logic-Embedded DRAms”,IEDM Technical Digest, (1998),pp. 347-350.
Vitkavage, S. C., et al., “An investigation of Si-SiO2 interface charges in thermally oxidized (100), (110), (111), and (511) silicon”,J. Appl. Phys., 68(10), (1990),pp. 5262-5272.

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