Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With specified crystal plane or axis
Reexamination Certificate
2001-05-08
2003-06-17
Niebling, John F. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With specified crystal plane or axis
C257S628000
Reexamination Certificate
active
06580154
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to integrated circuits, and more particularly, to a method, a structure and a system for providing semiconductor devices on (110) surfaces with conduction in the <110> direction.
BACKGROUND OF THE INVENTION
In general, the standard silicon wafer crystal orientation for VLSI (Very Large Scale Integration) is the (100) orientation. This surface orientation was chosen over the previously used (111) crystal orientation because of its comparatively low surface state density on thermally oxidized surfaces. In particular, a (111) crystal orientation has a surface state charge density of approximately 5×10
11
e/centimeters
2
(cm
2
) in comparison with a (100) crystal orientation which has a surface state charge density of approximately 9×10
10
e/cm
2
.
Surface state density was a particularly important consideration for n-channel Metal Oxide Semiconductor (NMOS) technologies because the higher this surface state density level the more difficult the controlling of active and parasitic device threshold voltages for devices using such technologies. For (110) surfaces, the surface state charge density is approximately 2×10
11
e/cm
2
which is approximately twice the density level for (100) surfaces. In present day technology, this difference in density levels translates into less than 0.09 volts offset in active device threshold voltage and is readily compensated by a surface threshold voltage ion implant. A further benefit to a lower surface state charge density for NMOS devices is that the electron mobility in inversion layers is greater on the (100) surface than on other lower order planes.
However, for modem day complimentary metal oxide semiconductor (CMOS) technology involving sub-micron devices, a different set of trade-offs are involved. For such short channel devices, the NMOS devices operate largely in velocity saturation resulting in a source to drain current which is independent of crystal orientation.
In contrast as illustrated in
FIGS. 1 and 2
, p-channel Metal Oxide Semiconductor (PMOS) devices are less likely to operate in velocity saturation, and therefore are more dependent on the choice of crystal orientation around inversion layer hole mobility. In particular,
FIG. 1
includes a transistor
100
, which can be either an NMOS or PMOS transistor. Transistor
100
is comprised of a silicon wafer
102
, a source region
104
, a drain region
106
, a gate
108
, an oxide layer
110
, a body region
111
and a channel region
112
between the source region
104
and the drain region
106
. As is well-known in the art, a voltage differential between the source region
104
and the drain region
106
induces an electric field across the channel region
112
. A gate potential applied to the gate
108
can create an inversion layer in the body region
111
allowing the channel region
112
to form between the source region
104
and the drain region
106
. This electric field is expressed in terms of the voltage differential between the source region
104
and the drain region
106
per the length of the channel region
112
.
FIG. 2
illustrates a graph of the drift velocity for carriers (i.e., either holes or electrons) across the channel region
112
, expressed in cm/second (sec), versus an average source-to-drain electric field, expressed in volts/cm. In particular, a plot
202
is the graphical plot of the drift velocity of electrons in the channel of an NMOS versus the electric field generated by the voltage differential between the source region
104
and the drain region
106
. Additionally, a plot
204
is the graphical plot of the drift velocity of holes in the channel of a PMOS versus the electric field generated by the voltage differential between the source region
104
and the drain region
106
. As illustrated, the plot
202
reaches velocity saturation at approximately 10
4
V/cm (i.e., the point in which the graphical plot flattens). In contrast in the graph of
FIG. 2
, the plot
204
has not reached the point of velocity saturation, even at 10
5
V/cm. Thus, a PMOS device that uses holes as carriers is more dependent on the choice of crystal orientation for inversion hole mobility.
Currently, surfaces with a (110) crystal plane orientation have been explored in the planar bulk and Silicon On Insulator (SOI) technologies by using (110) substrate wafers or causing the recrystallization of the surface of a substrate wafer to have a (110) crystal orientation. However, these structures and methods require re-tooling of crystal growth mechanisms used in conjunction with the standard (100) crystalline plane orientation and/or otherwise introduce costly, additional processing steps and procedures.
Thus, there is a need for structures and methods which improve carrier mobility in semiconductor devices and which do so without the introduction of costly additional processing steps or which require any re-tooling of standard crystal growth mechanisms. For these and other reasons there is a need for the present invention.
SUMMARY OF THE INVENTION
The above-mentioned problems and limitations associated with carrier mobility in semiconductor devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Structures and methods are described which accord improved benefits.
Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation in which an electrical current of such structures is in a <110> direction. Advantageously, improvements in carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.
Embodiments of a method of forming an integrated circuit include forming a trench in a silicon wafer. A trench wall of the trench has a (110) crystal plane orientation. A semiconductor device is also formed lateral to the trench wall such that the semiconductor device is capable of conducting an electrical current in a <110> direction.
One method of the present invention provides for forming an integrated circuit. Another method includes forming an integrated circuit including an array of MOSFETs while another method includes forming an integrated circuit including a number of lateral transistors. Another method includes forming a semiconductor device. Moreover, other embodiments provide for forming MOSFET devices (e.g., PMOS and NMOS devices). The present invention also includes structures as well as systems incorporating such structures all formed according to the methods provided in this application.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
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patent:
Forbes Leonard
Noble Wendell P.
Reinberg Alan R.
Dickey Thomas L
Micro)n Technology, Inc.
Niebling John F.
Schwegman Lundberg Woessner & Kluth P.A.
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