Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-15
2006-08-15
Lin, Sun James (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07093226
ABSTRACT:
To exam mask defect impact during the transfer of a mask pattern to a wafer layer, tools can use mask images obtained during mask inspection. Specifically, these tools can also use optical models of such mask images to simulate wafer images. However, when feature sizes become very small, optical models may not provide sufficiently accurate simulation results. Using a photoresist model would yield significantly more accurate simulation results than using an optical model. Unfortunately, resist modeling is very slow, thereby making it commercially impractical. A simulation tool can generate a simulated wafer image having the accuracy of a photoresist model with the speed of an optical model by using a threshold look-up table. In one embodiment, the threshold look-up table could include variables such as feature size, pitch size, feature type, and defect type.
REFERENCES:
patent: 5965306 (1999-10-01), Mansfield et al.
patent: 6289499 (2001-09-01), Rieger et al.
patent: 6577994 (2003-06-01), Tsukuda
patent: 2002/0164065 (2002-11-01), Cai et al.
patent: 2002/0194576 (2002-12-01), Toyama
patent: WO 01/65317 (2001-09-01), None
Bruner et al. “Simple Models for Resist Processing Effects”, Jun. 1996, Penn Well Publishing, Solid State Technology, vol. 39, iss. 6, pp. 95-99.
Peng et al., “Direct Interferometric Phase Measurement Using Aerial Image Measurrement System”, Mar. 1999, SPIE Conference on Metrology, Inspection, and Process Control for Microlithography XIII, SPIE vol. 3677, pp. 734-739.
Lu et al. “Application of Simulation Based Defect Printability Analysis for Mask Qualification Control,” Proceeedings of the SPIE, vol. 5038, Feb. 2003, p. 33-40.
Pang et al. “Simulation-based Defect Printability Analysis on Alternating Phase Shifting Masks for 193 nm Lithography,” Proceedings of the SPIE, vol. 4889, Oct. 2002, p. 947-954.
Randall et al. “Variable Threshold Resist Models for Lithography Simulation,” Proceedings of the SPIE, vol. 3679, Mar. 1999, pp. 176-182.
Bever Hoffman & Harms LLP
Harms Jeanette S.
Lin Sun James
Synopsys Inc.
LandOfFree
Method and apparatus of wafer print simulation using hybrid... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus of wafer print simulation using hybrid..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus of wafer print simulation using hybrid... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3648414