Method and apparatus of stress relief in semiconductor...

Details Method and apparatus of stress relief in semiconductor... Method and apparatus of stress relief in semiconductor...

2008-05-06

2008-05-06

Dickey, Thomas (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

With means to control surface effects

Insulating coating

C257S637000, C257S640000, C257SE23145, C257SE23167

Reexamination Certificate

active

07368804

ABSTRACT:
A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.

REFERENCES:
patent: 6486059 (2002-11-01), Lee et al.
patent: 6638849 (2003-10-01), Ting et al.
patent: 6972209 (2005-12-01), Agarwala et al.
patent: 2003/0042580 (2003-03-01), Hoinkis et al.
patent: 2003/0214041 (2003-11-01), Suzuki et al.
patent: 2004/0087135 (2004-05-01), Canaperi et al.

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