Method and apparatus of reducing transfer latency in an SOC...

Details Method and apparatus of reducing transfer latency in an SOC... Method and apparatus of reducing transfer latency in an SOC...

2007-08-28

2007-08-28

Lee, Christopher E. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S110000, C710S241000, C710S244000, C709S211000

Reexamination Certificate

active

11027532

ABSTRACT:
Embodiments of the invention are directed to a method and apparatus for reducing transfer latency in a system on a chip, the system on a chip comprising a bus master, a bus slave and an arbiter, wherein the bus master, bus slave and arbiter are in electronic communication therebetween. A request is transmitted from the bus master to the arbiter, wherein a priority signal is associated with a latency requirement. The arbiter reviews the latency requirement prior to transmitting the request to the bus slave and determines whether to elevate the priority signal. The request signal is then transmitted from the arbiter to the bus slave. The bus slave fulfills the request and transmits a response to the request, wherein the transmission includes the priority signal.

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