Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-06-19
2004-10-26
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06810513
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuit performing digital processing functions. More specifically, the present invention relates to the signal routing in the integrated circuit.
BACKGROUND
Circuit designers today typically have a variety of approaches to implement their desirable logical functions. An approach involves incorporating their designs in dedicated custom integrated circuits, also known as custom designs. Another approach involves the implementation of application-specific integrated circuits (“ASICs”). For these approaches, the initial costs are typically high and the turn-around time for producing a first set of these semiconductor chips are relatively long. An alterative approach, which enjoys growing popularity, is utilizing programmable circuit devices, such as programmable logic devices (“PLDs”), or field programmable gate arrays (“FPGAs”), hereinafter referred to as PLD. The circuit designers can program a PLD or PLDs to perform their desirable logical functions.
A PLD is a semiconductor chip that typically includes an array of programmable logic array blocks (“LABs”), routing resources, and input/output (“I/O”) pins. Each LAB may further include multiple programmable logic elements (“LEs”). For example, a LAB consists of 16 LEs, wherein each LE can be specifically programmed to perform a function or a set of functions.
A typical routing resource in a PLD is organized in a multiple banks of routing circuits, such as routing multiplexers or selectors. Each bank typically contains a finite number of multiplexers for routing various signals between I/O pins and feedbacks. For example, a routing resource contains four banks and each bank contains nine multiplexers. Accordingly, a bank of routing circuits can route at most nine signals simultaneously. A problem may arise when a bank tries to route more signals than its routing multiplexers. As the previous example illustrated, the routing would fail if the bank with nine multiplexers tries to route ten signals at a given time. The routing failure typically leads to device configuration failure.
Thus, what is needed is a mechanism to enhance the routing resources for PLD.
SUMMARY OF THE INVENTION
A technique for signal routing in an integrated circuit (“IC”) is disclosed. In one embodiment, the IC is a programmable logic device (“PLD”), wherein the PLD includes a logic block, a control block, and a routing block. The logic block further includes multiple logical array blocks (“LABs”). Each LAB is organized to contain various programmable logic elements, which can be individually configured to perform one or more specific logic functions. The routing block further includes a programmable interconnection array (“PIA”), which can be configured to transmit various signals between LABs and input/output pins. In one embodiment, PIA includes a first bank or routing array (“RA”), which has at least one configurable multiplexer and one output circuit and a second bank or RA, which also has one configurable multiplexer and one output circuit. The configurable multiplexer of the first bank can be programmed to route a signal to the logic block via the output circuit of the second bank. The configurable multiplexer is programmable to route its output signal through its neighboring bank.
Additional features and benefits of the present invention will become apparent from the detailed description, figures and claims set forth below.
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patent: 5594364 (1997-01-01), Chan et al.
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patent: 5689195 (1997-11-01), Cliff et al.
Altera Corporation
Altera Corporation
Lin Sun James
Siek Vuthe
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