Method and apparatus of optimizing the IO collar of a...

Details Method and apparatus of optimizing the IO collar of a... Method and apparatus of optimizing the IO collar of a...

2007-09-04

2007-09-04

Do, Thuan V. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10907499

ABSTRACT:
An apparatus and method for optimizing the size of an IO collar and reducing the die size of an IC chip is provided. The method and apparatus includes arranging rotated IO cells around the edges of the IC chip to reduce the number of unused IO cells in the IO collar. All the IO cells may be rotated, or a combination of rotated and non-rotated IO cells may form the IO collar. For each edge of the IC chip having rotated IO cells, each edge may have the same number of stacks of IO cells or a different number of stacks of IO cells.

REFERENCES:
patent: 6163042 (2000-12-01), Mizushima et al.
patent: 6457157 (2002-09-01), Singh et al.
patent: 6721933 (2004-04-01), Iwasa
patent: 7194707 (2007-03-01), Chung-Maloney et al.
patent: 2003/0137861 (2003-07-01), Thies et al.
patent: 8-96022 (1996-04-01), None
patent: 9-321142 (1997-12-01), None
patent: 2000-100955 (2000-04-01), None
English Language Abstract of JP 2000-100955.
English Language Abstract of JP 9-321142.
English Language Abstract of JP 8-96022.

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