Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2005-07-19
2005-07-19
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C714S711000, C714S718000, C365S049130, C365S052000, C365S200000, C365S230060, C711S108000
Reexamination Certificate
active
06920525
ABSTRACT:
A local word-line redundancy architecture and method that implements both word-line and match-line steering for semiconductor memories and more particularly for content-addressable memories (CAM) are introduced. According to the present invention, the method of performing local word-line redundancy comprising: testing by using BIST, storing results, comparing failing read address data and failing match-line address data to determine if redundancy is possible and, if so, storing the redundancy repair data pattern and loading that patten upon initialization so that redundancy steering is activated.
REFERENCES:
patent: 6137707 (2000-10-01), Srinivasan et al.
patent: 6275406 (2001-08-01), Gibson et al.
patent: 6286116 (2001-09-01), Bhavsar
patent: 6728123 (2004-04-01), Batson et al.
Chadwick Thomas B.
Gordon Tarl S.
Nadkarni Rahul K.
Ouellette Michael R.
Rowland Jeremy
International Business Machines - Corporation
Namazi Mehdi
Padmanabhan Mano
Walsh Robert A.
Whitham Curtis & Christofferson, P.C.
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