Method and apparatus of fabricating a semiconductor device...

Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...

Reexamination Certificate

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Details

C257SE21596, C257SE21599, C438S114000, C438S465000, C438S113000, C438S458000, C438S464000, C438S462000, C438S460000

Reexamination Certificate

active

07495315

ABSTRACT:
A method and apparatus of fabricating a semiconductor device by back grinding and dicing is disclosed. The method may include at least adhering a protection tape for back grinding on a front surface of a semiconductor wafer, back grinding a rear surface of the semiconductor wafer while the protection tape faces downward, loading the semiconductor wafer to dicing equipment when the front surface having the protection tape faces downward, detecting a dicing position formed on the front surface of the semiconductor wafer, and dicing the semiconductor wafer with the protection tape adhering thereon into individual semiconductor chips in accordance with the detected dicing position. The dicing equipment may have a transparent aligning part for aligning the semiconductor wafer and a chuck part for supporting the semiconductor wafer.

REFERENCES:
patent: 6338980 (2002-01-01), Satoh
patent: 6448151 (2002-09-01), Tateishi
patent: 6716723 (2004-04-01), Nepomuceno et al.
patent: 2002/0048904 (2002-04-01), Oka
patent: 2000-208446 (2000-07-01), None
patent: 2000-306875 (2000-11-01), None
patent: 2003-0091648 (2003-12-01), None

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