Method and apparatus of core timing prediction of core logic...

Details Method and apparatus of core timing prediction of core logic... Method and apparatus of core timing prediction of core logic...

2006-04-28

2010-06-15

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07739639

ABSTRACT:
A method and/or an apparatus of core timing prediction is disclosed. In one embodiment, a method may include generating a core timing model of a core logic that is accurately transferable to any chip-level integration process. The method may reduce performance degradation and/or performance variation of the core logic caused by a number of interactions between core logic components and chip-level components in the chip-level integration process. In addition, the core timing model of the core logic may be generated by filling un-wired tracks with metal in any of an outermost layer of the core logic after a core logic routing and constructing a layer at least an area of and adjacent to any of the outermost layer of the core logic with grounded metal that is orthogonal to those of the metal used in the outermost layer of the core logic.

REFERENCES:
patent: 6613611 (2003-09-01), How et al.
patent: 7112994 (2006-09-01), Madurawe
patent: 7379855 (2008-05-01), Oda et al.

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