Method and apparatus of controlling memory device

Details Method and apparatus of controlling memory device Method and apparatus of controlling memory device

2004-10-20

2008-03-04

Peugh, Brian R. (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

C711S002000, C711S170000

Reexamination Certificate

active

07340583

ABSTRACT:
An address decoder10decodes an address signal20to generate access signals22, 24. An OR circuit implements a logical OR of the signals22, 24to generate a chip enable signal. An address generation circuit14generates an address signal28to access the RAM in ascending order from a head address based upon the signal20. An address inversion circuit16inverts and outputs each bit of the signal28when the signal24is “1” or outputs the address signal without inversion when the signal24is “0.” When the chip enable signal is “1,” the RAM performs reading/writing data according to an address signal30from the inversion circuit.

REFERENCES:
patent: 5708842 (1998-01-01), Ikegaya et al.
patent: 6480936 (2002-11-01), Ban et al.
patent: 07-105081 (1995-04-01), None

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