Method and apparatus of a smart decoding scheme for fast...

Details Method and apparatus of a smart decoding scheme for fast... Method and apparatus of a smart decoding scheme for fast...

2006-11-28

2006-11-28

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S100000, C711S154000

Reexamination Certificate

active

07143257

ABSTRACT:
An apparatus and method identify a plurality of words to be read, read these selected words during a clock latency period, and then shift these words out synchronously at an end of the latency period. In another aspect of the present invention, the above method of reading a plurality of words during a clock latency period and shifting them out synchronously after the latency period is facilitated by a two tier column decoder. The two-tier column decoder has two decoders. A first-tier decoder decodes a first group of words to be read during the latency period, and a second-tier decoder decodes subsequent words to be shifted out synchronously during a burst period.

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