Method and apparatus in a communication receiver for adjusting a

Pulse or digital communications – Testing – Data rate

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375365, H04B 1700, H04L 704

Patent

active

059740868

ABSTRACT:
A method (600) that adjusts, at a predetermined boundary of a protocol utilized in decoding information from a signal received by a receiver (122), a symbol rate of the protocol (400). A processor (208) loads into a programmable counter (306), before a first boundary (412) of the protocol (400), a count of clock cycles defined to be received in the signal between the first and predetermined boundaries (414). The counter (306) counts from the first boundary (412), for a number of clock cycles equal to the count, a recovered bit clock synchronized with the signal and having the bit rate of the signal, to detect an occurrence of the predetermined boundary (414). The processor (208) loads, between the first (412) and predetermined boundaries (414), the another symbol rate into a bit-rate selection circuit (304). An output symbol rate of the bit-rate selection circuit (304) is enabled upon detecting the occurrence of the predetermined boundary (414), thereby adjusting the output symbol rate to the other symbol rate at the predetermined boundary (414).

REFERENCES:
patent: 5111486 (1992-05-01), Oliboni et al.
patent: 5168493 (1992-12-01), Nelson et al.
patent: 5425056 (1995-06-01), Maroun et al.
Anselm Sequelra, "Circuit To Change Clock Speed Without Loss Of Timing", Motorola, Inc. Technical Developments Vol. 19 Jun. 1993, p. 122.

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