Method and apparatus implementing a FIFO with discrete blocks

Details Method and apparatus implementing a FIFO with discrete blocks Method and apparatus implementing a FIFO with discrete blocks

2000-05-09

2004-08-17

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral adapting

C710S029000, C710S033000, C710S039000, C710S040000, C710S052000, C710S105000

Reexamination Certificate

active

06779061

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and/or architecture for data transfer generally and, more particularly, to a method and/or architecture for data transfer through a quantum FIFO.
BACKGROUND OF THE INVENTION
First-in-first-out (FIFO) buffers are used to transfer data between a system (domain) operating at a first clock rate and a system (domain) operating at a second clock rate. In a conventional FIFO, data is written to a memory according to a write pointer and read from the memory according to a read pointer. The write and read pointers need to be managed to provide overwrite and underwrite protection.
Referring to
FIG. 1
, a block diagram of a circuit
10
illustrating data flow in a conventional Universal Serial Bus (USB) chip is shown. Conventional USB chips transfer USB serial data between a first clock domain (i.e., serial bus
12
) and an endpoint FIFO
14
. The data reaches a second clock domain (i.e., the external interface
16
) via programmed transfers through a microprocessor
18
. The conventional USB chip
10
provides a low cost, low performance approach suited to low speed systems such as USB mice and keyboards.
Referring to
FIG. 2
, a block diagram of a circuit
20
illustrating a faster conventional approach is shown. For higher transfer rates, an interface FIFO
22
can reconcile the first clock domain (i.e., the serial bus
12
′) and the second clock domain (i.e., the external interface
16
′). The circuit
20
can provide a higher data transfer rate than the circuit
10
because the microprocessor
18
′ does not participate in the data transfer between the FIFOs
14
′ and
22
.
Because of the transfer times (FIFO-microprocessor and FIFO-FIFO), the conventional circuits
10
and
20
are not fast enough to economically sustain a data rate of 480 Megabits per second as required by newer bus standards (e.g., USB 2.0, the Universal Serial Bus Specification 2.0, which is hereby incorporated by reference in its entirety). Connecting a standard FIFO directly between the serial bus
12
and the external interface
16
requires extra tag bits to identify data as belonging to a particular endpoint. Also, a standard FIFO does not provide multi-port access to the external interface
16
′ and the microprocessor
18
′. In addition, a standard FIFO can not accommodate the packetized nature of USB data. For example, a USB OUT transfer sends data from a USB host (usually a PC) to an endpoint FIFO of a USB peripheral. After a full packet of data is received, the USB peripheral checks the packet for errors using a Cyclic Redundancy Check (CRC) and other methods. If errors are found, the USB peripheral suppresses an acknowledge signal to indicate to the USB host that the data must be re-transmitted. In a standard FIFO, the external interface can clock out some of the bad data before the USB peripheral detects the error. Recalling erroneous data from a standard FIFO is difficult.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising one or more storage elements configured to switch between a first domain and a second domain in response to one or more control signals.
The objects, features and advantages of the present invention include providing a method and/or architecture for a quantum FIFO that may (i) provide a low cost solution to providing very high bandwidth transfers, (ii) eliminate the internal movement of data bytes, (iii) instantaneously switch discrete FIFO blocks between USB and input/output domains, (iv) provide a FIFO with a zero transfer time, (v) use multiple small single or multi-port RAMs, (vi) allow single and dual-port RAMs to be used as dual and triple-port RAMs, respectively, (vii) eliminate read/write and read/read collision logic, (viii) provide an architecture that uses multiple addressable FIFOs (e.g., USB where the FIFOs are called endpoints), (ix) guarantee that FIFO data presented to external logic is error free, and/or (x) allow a microprocessor or micro-controller to associate packets with particular output FIFOs based on packet data.


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